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SystemVerilog-based Verification Environment using SystemC Constructs  

Oh, Young-Jin (충북대학교)
Song, Gi-Yong (충북대학교)
Publication Information
Journal of the Institute of Convergence Signal Processing / v.12, no.4, 2011 , pp. 309-314 More about this Journal
Abstract
As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.
Keywords
SystemVerilog; SystemC; verification environment; layered testbench; OOP; multiple inheritance;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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