• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.1
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• pp.123-129
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• 2023

In this paper, the frequency synthesis(FS) MMIC and the receive MMICs were developed for a Ka-band compact radar. Also a compact Ka-band frequency synthesizer and a receiver were developed based on those MMICs. The FS MMIC and the wireless-receiver(WR) MMIC to receive the baseband frequency were manufactured by a 65 nm CMOS process and the front-end(FE) MMIC to receive the Ka-band frequency was manufactured by a 150 nm GaN process. Linear frequency modulation waveform and pulse waveform for the transmit signal were measured by output signal of frequency synthesizer. The measured performance of developed receiver including the FE MMICs and the WR MMIC were ≧ 80 dB gain, ≦ 6 dB noise figure and ≧ 10 dBm at OP1dB. The measurement results of the developed frequency synthesizer and the receiver including the manufactured MMICs showed that they could be applied to Ka-band compact radar.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1872-1879
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• 1994

The design and implementation of Ku-Band frequency synthesizer was accomplished by the use of PLL and frquency multiple method. Design procedure and operation characteristics of PLL circuit were analyzed on the basis of control theory to synthesize about 1 GHz frequency which should be stable. By connecting frequency doubler and frequency eighth multiplier to the designed PLL circuit in series, Ku-Band frequency was synthesized. The validity of design method of Ku-Band frequency synthesizer was verified through experimental results.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.141-144
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• 2015

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.482-484
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• 2006

This paper describes fast-hopping frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432MHz, 3960MHz, 4488MHz) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224MHz. The second uses three PLLs operating at corresponding center frequencies. The third employes two PLLs operating at 3960MHz and 528MHz. Simulation results using a 0.18um RF CMOS process parameters show that the third structure exhibit the best characteristics. The band switching time of the proposed synthesizer is less than 1.3ns and the spur is less than -36dBc. The synthesizer consumes 22mA from a 1.8V supply.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.485-487
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• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.7
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• pp.18-27
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• 1997

A CMOS 950 MHz frequency synthesizer is designed and fabricated in a 0.8.mu.m standard CMOS process for IS-95-A CDMA mobile communication transceivers To utilize a CMOS ring VCO in a CDMA wireless communication receisver, we employed a QDC (quasi-direct conversion) receiver architecture for CDMA applications. Realized RF frequency synthesizer used as the RF local oscillator for a QDC receiver exhibits a phase noise of -92 dBc/Hz at 885kHz offset from the 950.4 MHz carrier, which complies with IS-95-A CDMA specification. It has a rms jitter of 23.7 ps, and draws 30mA from a 5V supply. Measured I/Q phase error of the 950.4 output signals is 0.7 degree.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2B
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• pp.151-159
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• 2002

Frequency synthesizer is an essential part for developing high speed frequency hopping radio. A high speed synthesizer using DDS driven PLL technique is designed and implemented for a X-band portable satellite terminal. It generates transmitter and receiver frequency ranging 6600∼7100MHz and 6140∼6640MHz, respectively by using 102.4MHz local oscillator, Its lock time is below 15 $\mu$sec and Its phase noise is below -754dBc at 1KHz offset Sequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.127-136
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• 1989

A Symbolic cover Minimization Algorithm and State CHDL Description for Finite State Machine Synthesizer are Presented. State CHDL are used for design of PLA based finite state machine, also the symbolic cover minimization algorithms are based upon single cube containment and distance 1 merging algorithms. The procedure for state machine synthesizer has been applied to practical example, including traffic light controller by using Boulder Optimal Logic Design System.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.816-820
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• 1990

A Tx modulator of the AMPS cellular wireless communication has been implemented using the PLL synthesizer, of which is modified for multiple frequency output capability. The frequency range is in 825-845 MHz with the 666 channels of 30KHz channel spacing and its switching time is less than 40 msec. The purpose of this paper is to develope the PLL frequency synthesizer with the high speed pulse swallow prescaler in order to save power consumption and cost. The PLL frequency synthesizer is studied in this paper to apply the cellular communication modulator.