• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.5
• /
• pp.232-242
• /
• 2005

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in BFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.4
• /
• pp.285-292
• /
• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.42 no.5
• /
• pp.430-436
• /
• 2014

The mission objective of STEP Cube Lab. (Cube Laboratory for Space Technology Experimental Project) classified as a pico-class satellite is to verify the technical effectiveness of payloads such as variable emittance radiator, SMA washer, oscillating heat pipe and MEMS based solid propellant thruster researched at domestic universities. In addition, the MEMS concentrating photovoltaic power system and the non-explosive holding and separation mechanism with the advantages of high constraint force and low shock level will be developed as the primary payloads for on-orbit verification. In this study, the feasibility of the mission actualization has been confirmed by the preliminary system design.

• Nuclear Engineering and Technology
• /
• v.48 no.4
• /
• pp.1047-1057
• /
• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.7 no.3
• /
• pp.95-99
• /
• 2008

This paper proposes a new minimal resource high-level synthesis algorithm for low power design automation. The proposed algorithm executes an efficient approach to minimize the power consumption of the functional units in a circuit during the high level synthesis. In this paper, we visit all control steps one by one to reduce the switching activity in CDFG. The register sharing algorithm determines the minimum register after the life time analysis of all variable. According to property of input signal for functional unit, the proposed method visits all control step one by one and determines the resource allocation with minimal power consumption at each control step in a greedy fashion. The effect of the proposed algorithm has been proved through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low rover.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.11 no.2
• /
• pp.161-169
• /
• 2011

This paper presents a new register transfer level synthesis methodology for efficient SOC system design. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system.

• 제어로봇시스템학회:학술대회논문집
• /
• 1999.10a
• /
• pp.92-95
• /
• 1999

The design problem of the control system is the ability to synthesize controller that achieve robust stability and robust performance. The paper explains the Finite Inclusions Theorem (FIT) by the procedure namely FIT synthesis. It is developed for synthesizing robustly stabilizing controller for parametrically uncertain system. The fundamental problem in the study of parametrically uncertain system is to determine whether or not all the polynomials in a given family of characteristic polynomials is Hurwitz i.e., all their roots lie in the open left-half plane. By FIT it can prove a polynomial is Hurwitz from only approximate knowledge of the polynomial's phase at finitely many points along the imaginary axis. An example shows the simplicity of using the FIT synthesis to directly search for robust controller of parametrically uncertain system by way of solving a sequence of systems of linear inequalities. The systems of inequalities are solved via the projection method which is an elegantly simple technique fur solving (finite or infinite) systems of convex inequalities in an arbitrary Hilbert space. Results from example show that the controller synthesized by FIT synthesis is better than by H$\sub$$\infty$/ synthesis with parametrically uncertain system as well as satisfied the objectives for a considerably larger range of uncertainty.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.3
• /
• pp.137-144
• /
• 2016

In this paper, we have proposed a circuit complexity optimization ILP algorithm of high-level synthesis system for new multiprocessor design. We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the ILP algorithm. We have achieved is that standard benchmark model for the scheduling of the 5th digital wave filter, it was exactly the same due to the existing datapath scheduling results.

• Bulletin of the Korean Chemical Society
• /
• v.24 no.12
• /
• pp.1819-1826
• /
• 2003

In connection with the studies for developing new enzymes that could be useful in organic synthesis, practical preparation of racemic and enantiopure forms of ${\gamma}$-hydroxy-${\alpha}$-keto acids has been successfully achieved. For racemic form of ${\gamma}$-hydroxy-${\alpha}$-keto acids, indium-mediated allylation of aldehydes with 2-(bromomethyl)acrylic acid has been employed as a key step. Oxidative cleavage of the thus formed 2-methylenebutyrolactones provided the desired ${\alpha}$-ketobutyrolactones. Enzymatic resolution of the ${\gamma}$-hydroxy-${\alpha}$-methylene esters provided the desired${\gamma}$-hydroxy-${\alpha}$-methylene acids which were successfully converted to ${\gamma}$-hydroxy-${\alpha}$-ketobutyrolactones in optically pure forms.

• Journal of electromagnetic engineering and science
• /
• v.16 no.2
• /
• pp.67-73
• /
• 2016

This paper presents simple expressions for the effective permeability of bulk metamaterial consisting of ring resonators (RRs) or split ring resonators (SRRs) based on the convenient geometrical factors of the structure compared with wavelength. The resonant frequency dependence of the medium permeability, including loss effects, is analyzed in detail. Inverting the analysis equations, useful design (or synthesis) equations are derived for a systematic design process with some examples. This paper may particularly be useful for the design of a bulk metamaterial with a specific negative relative permeability at a desired frequency. The loss of metamaterials consisting of RRs (or SRRs) is also analyzed over a wide frequency band from 10 MHz to 10 THz.