• The Transactions of the Korea Information Processing Society
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• v.6 no.9
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• pp.2548-2557
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• 1999

As the size of the FPD(Flat Panel Display) becomes larger and its resolution is higher, it is required a new controller to support these specifications. In this paper, we have designed a universal controller of a-Si TFT LCD which will dominate the future market. We propose a new type of a LCD controller, which is constructed by four-line parallel-bus architecture and can enlarge low resolution images to SXGA class images by using a new interpolation algorithm. The proposed LCD controller has been simulated and synthesized by using Synopsys VHDL.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10a
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• pp.735-738
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• 2001

디지털 캠코더에서 이용하는 영상 압축 방식인 DV 부호화방식은 DCT와 가변장 부호화 방식을 이용한다. DV 방식은 하드웨어 복잡도가 낮은 반면 압축된 비트 율이 약 26Mbps로 높은 편이다. 따라서 스튜디오에서 낮은 복잡도로 영상을 부호화 한 후 VOD 시스템에서 이용하기 위하여 MPEG-2로 변환부호화 할 필요가 있다. 이때의 두 압축방식이 DCT를 이용하므로, DCT영역에서 변환부호화 하면 중간과정을 줄일 수 있어서 계산상의 복잡도를 줄일 수 있다. 본 논문에서는 DV방식에서 MPEG-2의 인트라로 변환부호화시, DV방식의 4:1:1 색차포맷을 MPEG-2의 4:2:2 색차 포맷으로 변환할 때 변환영역에 있는 데이터에 미리 계산된 행렬을 곱하여 병렬처리가 가능하게 설계하였다. 또한 MPEG-2 율제어는 중요한 서브 블록의 분산을 완전히 DCT영역에서 계산하여 하드웨어 복잡도를 줄였다. 색차포맷변환부 하드웨어 구현을 위하여 VHDL로 코딩한 후 FPGA-EXPRESS(synopsys), ALTERA MAX-PLUS II를 사용하여 모의실험을 하였다. 각 모듈별로 기능을 검증한 후, FPGA EXPRESS(synopsys)를 사용하여 합성 및 검증을 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.181-189
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• 2001

In this thesis, a policing algorithm is proposed, which is one of the traffic management function in ATM networks. The proposed algorithm minimizes CLR(Cell Loss patio) of high priority cells and solves burstiness problem of the traffic caused by multiplexing and demultiplexing process. The proposed algorithm has been implemented with VHDL and is divided into three parts, which are an input module, an UPC module, and an output module. In implementation of the UPC module\`s memory access, memory address is assigned according to VCI\`s LSB(Lowest Significant Byte) of ATM header for convenience. And the error of VSA operation from counter\`s wrap-around can be recovered by the proposed method. ANAM library 0.25 $\mu\textrm{m}$ and design compiler of Synopsys are used for synthesis of the algorithm and Synopsys VSS tool is used for VHDL simulation of it

• Journal of IKEEE
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• v.23 no.1
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• pp.338-341
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• 2019

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.1
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• pp.115-126
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• 1999

As the processing speed of communication and computer system has been improved, high speed data processing is required to correct error of data. In this paper, decoding algorithm which is applicable to the wireless communication system is proposed and encoder and decoder are designed by using the proposed decoding algorithm. We design the encoder and decoder by using the VHDL(VHSIC Hardware Description Language) and simulate the designed encoder and decoder by using V-system. Designed algorithm is synthesized by using synopsys tools and is made to one chip by means of XILINX XC4010EPC84-4. When 20MHz was used as the input clock, data arrival time was 29.20ns and data require time was 48.70ns.

• Journal of IKEEE
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• v.25 no.1
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• pp.168-173
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• 2021

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

• Journal of IKEEE
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• v.26 no.1
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• pp.119-123
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• 2022

This paper propose a new ESD protection device suitable for 12V class applications by adding a self-biasing structure to an ESD protection device with high holding voltage due to additional parasitic bipolar BJT. To verify the operating principle and electrical characteristics of the proposed device, current density simulation and HBM simulation were performed using Synopsys' TCAD Simulation, and the operation of the additional self-biasing structure was confirmed. As a result of the simulation, it was confirmed that the proposed ESD protection device has a higher level of holding voltage compared to the existing ESD protection device. It is expected to have high area efficiency due to the dual structure and sufficient latch-up immunity in 12V-class applications.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.83-97
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• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.303-306
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• 2000

In this paper, we propose VC merge capable hardware architecture for scalability based on ATM switching fabric. We implemented a scheduler for configuring crossbars in input-queued switches which support virtual output queues at the input ports. Also, we implemented VC merge capable scheduler at the output ports. We verified the proposed model by using C language, and designed with VHDL language. Then, we simulated and synthesized it with software of the SYNOPSYS corporation.