• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.78-81
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• 1999

The position and time errors of a conventional L1-band GPS receiver (1575.42MHz) are known to be about 100 m and 70 ns, respectively. These errors are mainly due to the propagation delay of GPS satellite signals through ionosphere. Various L1/L2 dual-band GPS receivers are normally used to compensate for those position and time errors by detecting an accurate propagation delay. These receivers detect the propagation delay difference between the L1 and L2 signals based on the fact that the propagation delay through ionosphere is dependent on frequency and, from which, calculate an accurate propagation delay of the GPS signals through ionosphere. In this paper, we analyzed the architecture of a L1/L2 dual-band CPS receiver by high-level simulations with Synopsys's COSSAP Tool.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.46-53
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• 1999

In this paper, a packer is proposed for removing the bottle-neck effect and processing easy signal using a new algorithm with the operation frequency of 54MHz in processing HDTV video signal. To verify the performance of the proposed packer, DCT coefficient encoding block with ROM table using a combinational logic is designed and its output data are used as the input data of the packer.The proposed circuits, in this paper, are designed by using VHDL code and its modeling and simulation are performed with SYNOPSYS tool in $0.65{\mu}m$ design rule.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.661-673
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• 2000

In this paper, we propose a Web-based HW/SW Codesign Environment with Distributed Architecture (WebCEDA), then design and implement SpecCharts Specification Environment(ScSE) for specifying systems in WebCEDA. WebCEDA has 3-tier client/server architecture than can remedy disadvantages of existing codesign tools, such as platform dependency, difficulty of extension, absence of collaboraton environment. ScSE includes web interface, SpecCharts editor, HW/SW codesin application sever and SpecCharts translator. To verify the operation of ScSE, we specify several example system using SpecCharts editor, then translate it to VHDL using SpecCharts translator and simulate the translated VHDL codes on synopsys. As the results, we know that ScSE has correct operations, also obtain the following advantages, the reduction in system complexity and the natural abstract design.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.11a
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• pp.151-156
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• 1997

본 논문은 저비용이면서 정확한 제어를 수행하는 새로운 퍼지 제어기의 VHDL 설계 및 FPGA 구현을 자동적으로 수행하는 통합 개발 환경(IDE : Integrated Development Environment)을 다룬다. 이를 위해 FLC의 자동 설계 및 구현의 전 과정을 하나의 환경 내에서 개발 가능하게 하는 퍼지 제어기 자동 설계 및 구현 시스템 (FLC Automatic Design and Implementation Station :FADIS)을 개발하였는데 이 시스템은 다음 기능을 포함한다. (1) 원하는 퍼지 제어기의 설계 파라메터를 입력받아 이로부터 FLC를 구성하는 각 모듈의 VHDL 코드를 자동적으로 생성한다. (2) 생성된 각 모듈의 VHDL 코드가 원하는 동작을 수행하는지를 Synopsys사의 VHDL Simulator상에서 시뮬레이션을 수행한다. (3) Synopsys사의 FPGA Compiler에 의해 VHDL 코드를 합성하여 FLC의 각 구성 모듈을 얻는다. (4) 합성된 모듈은 Xilinx사의 XactSTep 6.0에 의해 최적화 및 배치, 배선이 이루어진다. (5) 얻어진 Xilinx rawbit 파일은 VCC사의 r2h에 의해 C 언어의 header 파일 형태의 하드웨어 object로 변환된다. (6) 하드웨어 object를 포함하는 응용 제어 프로그램의 실행 파일을 재구성 \ulcorner 능한 FPGA 시스템 상에 다운로드한다. (7) 구현된 FLC의 동작 과정은 구현된 FLC와 제어 target 사이의 상호 통신에 의해 모니터링한다. 트럭 후진 주차 제어에 사용하는 퍼지 제어기 설계 및 구현의 전 과정을 FADIS상에서 수행하여 FADIS가 완전하게 동작하는지를 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.57-64
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• 2000

In this paper, we propose the new hardware architecture which implements the stereo matching algorithm using the dynamprogrammethod. The proposed MOEPE(Merged Odd-Even PE) architecture operates in the systolic manner and finds the disparities form the intensities of the pixels on the epipolar line. The number of PEs used in the MOEPE architecture is the same number of the range constraint, which reduced the nuMber of the necessary PEs draMatically compared to the traditional method which uses the PEs with the same number of pixels on the epipolar line. For the normal sized images, the numof the MOEPE architecture is less than that of the PEs in the traditional method by 25${\times}$The proposed architecture is modeled with the VHDL code and simulated by the SYNOPSYS tool.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.49-56
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• 2010

In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.648-651
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• 2001

This paper describes the 8-error-correction (204, 188) Reed-Solomon Decode. over GF(2$^{8}$ ) for a satellite communication. It is synthsized using a CMOS library. Decoding algorithm of Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to slove error-values. The decoder is designed using Modified Euclid algorithm in this paper. First of all, The functionalities of the circuit are verified through C++ programs, and then it is designed in Verilog HDL. It is verified through the logic simulations of each blocks. Finally, The Reed-Solomon Decoder is synthesized with Synopsys Tool.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1506-1511
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• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.156-162
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• 2003

With the network environment and user's application service increasing information protection and private information protection fields are very important fields. But it is necessary detection methodology to unspecified unknown signal, information increasing and various information media. Therefore in this thesis, we design NIDS that classify others information for detection of the unknown signal as the unauthenticated signal or illegal outer access, etc. proposed NIDS design used Synopsys Ver. 1999 and VHDL. The proposed NIDS system is practical in the system performance and cost for the individually existed NIDS, and utilized a part of system resources.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.973-979
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• 2002

In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed the multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.