• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.10
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• pp.1-7
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• 2020

In recent years, as LED display systems are actively spread, study on effective control methods for an LED driver for driving the systems has been in progress. The most representative among them is the uniform brightness control method for the LED driver channel. In this paper, we propose an LED driver IC for BLU with current compensation and system protection functions to minimize channel luminance deviation. It is designed for current accuracy within ±3% between channels and a channel current of 150 mA. In order to satisfy the design specifications, the channel amplifier offset was canceled out by a chopping operation using a channel-driving PWM signal. Also, a pre-charge function was implemented to minimize the fast operation speed and luminance deviation between channels. LED error (open, short), switch TR short detection, and operating temperature protection circuits were designed to protect the IC and BLU systems. The proposed IC was fabricated using a Magnachip 0.35-um CMOS process and verified using Cadence and Synopsys' Design Tool. The fabricated LED driver IC has current accuracy within ±1.5% between channels and 150-mA channel output characteristics. The error detection circuits were verified by a test board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.91-97
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• 2000

With the brilliant development of information communication and the rapid spread of internet, current network communication is carrying several up-to-date functions such as electronic commerce, activation of electro currency or electronic signature and will produce more advanced services in the future. Information communication network such as that electronic commerce would demand the more safe and transparent guard of network, and anticipate the more fast performance of network. In this paper, in order to meet the several demands, DES(data encryption standard) with parallel feistel structure, which feistel structure of the basic structure of DES is transformed into in parallel, is proposed. The existing feistel structure can't use pipeline method for the structural problem of DES itself-the propagation of error. therefore, this modified parallel feistel structure could improve largely the performance of DES which had to have the trade-off relation between data processing speed and data security and in addition a method proposed in SEED having adopted the modified parallel feistel structure shows more excellent secure function and/or fast processing ability. The used CAD Tool use Synopsys Ver. 1999. 10 in both of synthesis and simulation.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2A
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• pp.177-183
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• 2009

In this paper, we propose an improved anti-collision algorithm. We have designed an anti-collision unit using this algorithm for the 18000-6 Type C Class 1 Generation 2 standard (Gen2). The Gen2 standard uses a Q-algorithm for incremental method on the Dynamic Slot-Aloha algorithm. It has basically enhanced performance over the Slot-Aloha algorithm. Unfortunately, there are several non-clarified parts: initial $Q_{fp}$ value, weighted C, and the ending point of the algorithm. If an incorrect value is selected, it causes degradation in performance. Thus we propose an improved anti-collision algorithm by clearly defining the vague parts of the existing algorithm. Simulation results showed an improved performance of up to 34.8% using an optimized value of C and the initial $Q_{fp}$ value. With the ending condition, performance is 34.7%. The anti-collision unit is designed using the Verilog HDL. The module was synthesized using Synopsys' Design Compiler and the TSMC $0.2{\mu}m$ standard cell library. The synthesized result yielded 3,847 gates, and was guaranteed under the proposed working frequency of 19.2MHz.

• Korean Journal of Optics and Photonics
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• v.29 no.1
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• pp.19-27
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• 2018

A change in object distance would generally change the magnification of an optical system. In this paper, we have proposed and designed a double-Gauss optical system with a fixed magnification and image surface regardless of any change in object distance, according to moving the lens groups a little bit to the front and rear of the stop, independently parallel to the direction of the optical axis. By maintaining a constant size of image formation in spite of various object-distance changes in a projection system such as a head-up display (HUD) or head-mounted display (HMD), we can prevent the field of view from changing while focusing in an HUD or HMD. Also, to check precisely the state of the wiring that connects semiconductor chips and IC circuit boards, we can keep the magnification of the optical system constant, even when the object distance changes due to vertical movement along the optical axis of a testing device. Additionally, if we use this double-Gauss optical system as a vision system in the testing process of lots of electronic boards in a manufacturing system, since we can systematically eliminate additional image processing for visual enhancement of image quality, we can dramatically reduce the testing time for a fast test process. Also, the Gaussian bracket method was used to find the moving distance of each group, to achieve the desired specifications and fix magnification and image surface simultaneously. After the initial design, the optimization of the optical system was performed using the Synopsys optical design software.

• Journal of IKEEE
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• v.13 no.1
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• pp.87-93
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• 2009

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.