• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.433-441
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• 1992

The new synchronous hierarchy with abase signal near 150Mbit/s will become the international standards. An asynchronous video signal will be transmitted in the synchronous network with stuffing synchronization technique. In this study an estimate of power spectrum and effective values of the stuffing jitter signals under the influence of system parameters were obtained. The results show that the real stuffing jitter is greater than the ideal stuffing jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2891-2898
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• 2014

It is feasible to develop a fault tolerant system through module level redundancy on the Integrated Modular Avionics (IMA). However, its great implementation complexity is one of important challenges when asynchronous hardware environment is naturally assumed. To solve this problem, Physically Asynchronous Logically Synchronous (PALS) on IMA has been proposed. But, it has adaptation problem by not addressing specific architecture for IMA system. In the paper, we propose how to synchronize the input data on the IMA system under primary/secondary redundancy architecture by referring to existing PALS. In the proposed scheme, we introduce window frame by considering rate monotonic scheduling and analyze the adequate the synchronization time. Finally, we verify the feasibility of the proposed design pattern through the systematic experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1498-1508
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• 2003

It is important to integrate an enterprise application for automating of the business process, which is responded by a flow of market environment. There are two categories of method that integrate enterprise applications. One is Synchronous Integration, and the other is Asynchronous Integration. EAI(Enterprise Application Integration) and Web service which of the asynchronous integration is focused in the automating method of the business process. After we construct the application integration for automating of the business process, we have to concern about managing of the business transaction. Many Organizations have proposed the process method of business transaction based on 2-phase commit protocol. But this method can't supply the phase that classify the transaction by transaction weight. In this Paper, we Propose an efficient method of transaction process for business transactions, which is composed by ‘Classify Phase’ that classify transactions. We called this model “3-Phase Commit Method Applied by Classify Phase”, we design this model to manage an resource of enterprise efficiently. The proposed method is compared by the method based on 2-Phase commit that could be a problem of management the resource of enterprise, and the advantage of this method is certified to propose the solution of that problem.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.121-126
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• 2018

IEEE 802.1 TSN TG is developing standards for end-to-end delay bounds and zero packet loss based on Ethernet technology. We focus on packet forwarding techniques. TSN packet forwarding techniques can be classified into Synchronous and Asynchronous framework. Synchronous approach allocates fixed time period for a class, yet is complex for large networks. Asynchronous approach provides delay guarantee by regulator-scheduler pair, yet is unnecessarily complex, too. We propose network components for TSN Asynchronous architecture, which remove the complexity of maintaining flow state for regulation decisions. Despite such a simplicity, the proposed architecture satisfies the TSN's delay requirements provided the limited high priority traffic's maximum packet length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5B
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• pp.421-429
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• 2006

In this paper, we suggest a new capability aware spanning tree(CAST) algorithm for Ethernet bridged network which consists of both legacy Ethernet bridges and synchronous Ethernet ones. The legacy spanning tree algorithm specified in IEEE 802.1D standard select root bridge and construct tree based on each bridge's identifier without consideration of each bridge's capability. Thus we note that if the legacy STP may assign a synchronous bridge as a root bridge, the bridge may become a bottleneck for asynchronous trafficbecause of bandwidth limitation for asynchronous traffic. In this paper, the CAST algorithm constructsmultiple spanning tree by using of bridge capability and makes different transmission path for each traffics, can removes this kind of defect. From the simulation results, we can see that the proposed CAST algorithm has better end-to-end delay performance than legacy spanning tree algorithm in high traffic load and multiple hops environment.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1917-1926
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• 2018

In view of the current state of the reserves of electric energy generated resources and the share of electric motors in electricity consumption, many researches and studies related to efficiency in electric motors are being made. The presented work is related to the Axial Flux Permanent Magnet Synchronous Motor (AF-PMSM), which has recently undergone significant work based on the development of magnet and motor technology. In this study, a novel AF-PMSM was designed analytically through Finite Element Method (FEM) which can be started by connecting to a line such as an asynchronous motor in a transient state and can operate with high efficiency and power factor after synchronization in steady state without the need for an expensive motor drive. According to the obtained FEM results, a design with an efficiency class of IE4 of 5.5 kW shaft power, a 4 poles motor was obtained. As a result, economic calculations indicate that the extra cost of the designed Line start AF-PMSM with respect to the asynchronous motor is rapidly compensated by energy saving due to a more efficient operation, especially constant speed operations. As a result of the analysis obtained, the targeted values are reached. For induction motors and radial flux permanent magnet synchronous motors, a good alternative motor that can operate with high efficiency and power factor has been obtained.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.205-212
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• 2017

Linux Foundation has announced a real-time kernel, called Zephyr, for IoT applications recently. Zephyr kernel provides synchronous and asynchronous IPC for data communication between threads. Synchronous IPC is useful for programming multi-threads that need to be executed synchronously, since the sender thread is blocked until the data is delivered to the receiver thread and the completion of data transfer can be known to two threads. In general, 'IPC execution time' is defined as the time duration between the sender thread sends data and the receiver thread receives the data sent. Especially, it is important that 'IPC execution time' in the synchronous IPC should be fixed in real-time kernel like Zephyr. However, we have found that the execution time of the synchronous IPC in Zephyr kernel increases in proportion to the number of threads executing in the kernel. In this paper, we propose a method to implement a fixed time synchronous IPC in Zephyr kernel using Direct Thread Switching(DTS) technique. Using the technique, the receiver thread executes directly after the sender thread sends a data during the remaining time slice of the sender thread and we can archive a fixed IPC execution time even when the number of threads executing in the kernel increases. In this paper, we implemented synchronous IPC using DTS in the Zephyr kernel and found the IPC execution time of the IPC is always 389 cycle that is relatively small and fixed.