• Journal of the Korean Society for Precision Engineering
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• v.18 no.2
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• pp.192-198
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• 2001

In this study, a methodology of synchronous control which can be applied to position synchronization of a two-axes driving system has been developed. The synchronous error is caused by model uncertainties and torque disturbance of each axis. To overcome these problems, the proposed synchronous control system has been composed of two speed controllers and one synchronous controller. The speed controllers based on PID control law are aimed at the following to speed reference. And the parameters of speed controllers have been designed in order that speed response of the second axis corresponds with one of first axis. Especially, considering to model uncertainties of each axis, the synchronous controller has been designed using H$\infty$ control theory. The controller eliminates the synchronous error by controlling speed of the second axis. The effectiveness of the proposed method has been verified through simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.206-212
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• 2006

Many image and video compression algorithms work by splitting the input image into blocks and producing variable-length coded bits for each block data. If variable-length coded data are transmitted consecutively, then the resulting coder is highly sensitive to channel errors. Therefore, most image and video techniques for providing some protection to the stream against channel errors usually involve adding a controlled amount of redundancy back into the stream. Such redundancy might take the form of resynchronization markers, which enable the decoder to restart the decoding process from the known state, in the event of transmission errors. The Error Resilient Entropy Code (EREC) is a well known method which can regain synchronization without any redundant information to convert from variable-length code to fixed-length code. This paper proposes an enhancement to EREC, which greatly improves its transmission ability for the compressed image quality without any redundant bits in the event of errors. The simulation result shows that the both objective and subjective quality of transmitted image is enhanced compared with the existing EREC at the same BER(Bit Error Rate).

• Journal of Positioning, Navigation, and Timing
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• v.6 no.1
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• pp.17-26
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• 2017

Latency occurs in RTK, where the measured position actually outputs past position when compared to the measured time. This latency has an adverse effect on the navigation accuracy. In the present study, a system that estimates the latency of RTK and compensates the position error induced by the latency was implemented. To estimate the latency, the speed obtained from an odometer and the speed calculated from the position change of RTK were used. The latency was estimated with a modified correlator where the speed from odometer is shifted by a sample until to find best fit with speed from RTK. To compensate the position error induced by the latency, the current position was calculated from the speed and heading of RTK. To evaluate the performance of the implemented method, the data obtained from an actual vehicle was applied to the implemented system. The results of the experiment showed that the latency could be estimated with an error of less than 12 ms. The minimum data acquisition time for the stable estimation of the latency was up to 55 seconds. In addition, when the position was compensated based on the estimated latency, the position error decreased by at least 53.6% compared with that before the compensation.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.85-92
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• 2017

Recently, electric propulsion systems are used for unmanned surface vehicle, fish finder boat, etc. Some of these propulsion systems can be constructed of two electric motors and propellers for advanced impellent force. In this case, the speed difference generated between two propellers, namely, the synchronous error has a bad influence on the energy efficiency and course error. In this study, a synchronous control system is designed to restrain synchronous error caused by disturbance and mismatched dynamic characteristics. The control system is composed of the reference model, pre-filters, speed controllers, and synchronous controllers. The reference model is used for calculating the decoupled synchronous error and control input for each propulsion system. The pre-filters and speed controllers are designed in order that the propulsion system may follow the reference signal without overshoot and input saturation. And the synchronous controllers are designed from the viewpoint of stable and quick synchronization through root locus mothed approach. Finally, the simulation results show that the designed control system is effective for the disturbance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.10
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1032-1041
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• 2007

The global navigation satellite system (GNSS), which is the core technique for the location based service, adopts the direct sequence/spread spectrum (DS/SS) as its modulation method. The success of a DS/SS system depends on the synchronization between the received and locally generated pseudo noise (PN) signals. As a step in the synchronization process, the tacking scheme performs fine adjustment to bring the phase difference between the two PN signals to zero. The most widely used tracking scheme is the delay locked loop with early minus late discriminator (EL-DLL). In the ideal case, the EL-DLL is the best estimator among various DLL. However, in the band-limited multipath environment, the EL-DLL has tracking bias. In this paper, the timing offset range of correlation function is divided into advanced offset range (AOR) and delayed offset range (DOR) centering around the correct synchronization time point. The tracking bias results from the following two reasons: symmetry distortion between correlation values in AOR and DOR, and mismatch between the time point corresponding to the maximum correlation value and the synchronization time point. The former and latter are named as the type I and type II tracking bias, respectively. In this paper, when the receiver has finite bandwidth in the presence of multipath signals, it is shown that the type II tracking bias becomes a more dominant error factor than the type I tracking bias, and the correlation values in AOR are not almost changed. Exploiting these characteristics, we propose a novel tracking bias mitigation scheme and demonstrate that the tracking accuracy of the proposed scheme is higher than that of the conventional scheme, both in the presence and absence of noise.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.3
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• pp.125-133
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• 2017

Time comparison is necessary for the verification and synchronization of the clock. Two-way satellite time and frequency (TWSTFT) is a method for time comparison over long distances. This method includes errors such as atmospheric effects, satellite motion, and environmental conditions. Ionospheric delay is one of the significant time comparison error in case of the carrier-phase TWSTFT (TWCP). Global Ionosphere Map (GIM) from Center for Orbit Determination in Europe (CODE) is used to compare with Bernese. Thin shell model of the ionosphere is used for the calculation of the Ionosphere Pierce Point (IPP) between stations and a GEO satellite. Korea Research Institute of Standards and Science (KRISS) and Koganei (KGNI) stations are used, and the analysis is conducted at 29 January 2017. Vertical Total Electron Content (VTEC) which is generated by Bernese at the latitude and longitude of the receiver by processing a Receiver Independent Exchange (RINEX) observation file that is generated from the receiver has demonstrated adequacy by showing similar variation trends with the CODE GIM. Bernese also has showed the capability to produce high resolution IONosphere map EXchange (IONEX) data compared to the CODE GIM. At each station IPP, VTEC difference in two stations showed absolute maximum 3.3 and 2.3 Total Electron Content Unit (TECU) in Bernese and GIM, respectively. The ionospheric delay of the TWCP has showed maximum 5.69 and 2.54 ps from Bernese and CODE GIM, respectively. Bernese could correct up to 6.29 ps in ionospheric delay rather than using CODE GIM. The peak-to-peak value of the ionospheric delay for TWCP in Bernese is about 10 ps, and this has to be eliminated to get high precision TWCP results. The $10^{-16}$ level uncertainty of atomic clock corresponds to 10 ps for 1 day averaging time, so time synchronization performance needs less than 10 ps. Current time synchronization of a satellite and ground station is about 2 ns level, but the smaller required performance, like less than 1 ns, the better. In this perspective, since the ionospheric delay could exceed over 100 ps in a long baseline different from this short baseline case, the elimination of the ionospheric delay is thought to be important for more high precision time synchronization of a satellite and ground station. This paper showed detailed method how to eliminate ionospheric delay for TWCP, and a specific case is applied by using this technique. Anyone could apply this method to establish high precision TWCP capability, and it is possible to use other software such as GIPSYOASIS and GPSTk. This TWCP could be applied in the high precision atomic clocks and used in the ground stations of the future domestic satellite navigation system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.3 s.309
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• pp.9-16
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• 2006

Many image and video compression algorithms work by splitting the image into blocks and producing variable-length code bits for each block data. If variable-length code data are transmitted consecutively over error-prone channel without any error protection technique, the receiving decoder cannot decode the stream properly. So the standard image and video compression algorithms insert some redundant information into the stream to provide some protection against channel errors. One of redundancies is resynchronization marker, which enables the decoder to restart the decoding process from a known state in the event of transmission errors, but its usage should be restricted not to consume bandwidth too much. The Error Resilient Entropy Code(EREC) is well blown method which can regain synchronization without any redundant information. It can work with the overall prefix codes, which many image compression methods use. This paper proposes EREREC method to improve FEREC(Fast Error-Resilient Entropy Coding). It first calculates initial searching position according to bit lengths of consecutive blocks. Second, initial offset is decided using statistical distribution of long and short blocks, and initial offset can be adjusted to insure all offset sequence values can be used. The proposed EREREC algorithm can speed up the construction of FEREC slots, and can improve the compressed image quality in the event of transmission errors. The simulation result shows that the quality of transmitted image is enhanced about $0.3{\sim}3.5dB$ compared with the existing FEREC when random channel error happens.