• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.25-32
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• 2006

We propose a new M-ary state-transition FSK modulator technique for enhancing demodulator's symbol timing recovery which can be applied to acoustic MODEM. In the previous technique, the demodulator's symbol timing performance can degrade when the sequences of same symbols are transmitted. This proposed method, because the transmission symbol changes in every single symbol period, increases the synchronization performance dramatically and has a simple MODEM and frame structure. On the one hand, we improve modulation-derived synchronization(MDS) which is M-ary FSK's symbol timing recovery scheme, then analyze it. Finally the proposed method is analyzed from the viewpoint of frequency efficiency, which proves this method is appropriate for acoustic MODEM.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.81-85
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• 1999

DWMT VDSL system needs A/D converter clock, bit clock, symbol clock, frame clock, etc. DMT ADSL system utilizes a correlation method which makes use of cyclic prefix or preamble pattern for clock recovery. But the correlation method is difficult to apply to the DWMT system because modulated symbols are overlapped in the time domain. This paper proposes a novel clock recovery method which can be used for the DWMT system due to its inherent independence of the modulation method. This new method is verified by SPICE simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1436-1444
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• 2000

In this paper, we propose the joint carrier and symbol timing recovery algorithm using repetitive preamble and differential detection for burst modem. The proposed algorithm can estimate the frequency offset and the symbol timing error regardless of the amount of frequency offset, with a high accuracy, even using very short preamble and at low SNR values. The algorithms for continuous phase frequency shift keying (CPFSK) and phase shift keying (PSK) types are developed. Through computer simulations, we compare the proposed algorithm with the existing algorithms on the estimation accuracy in terms of the preamble length, and analyze those bit error rate(BER) performance.

• Journal of the Optical Society of Korea
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• v.13 no.3
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• pp.367-372
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• 2009

In this paper we propose an electronic domain timing phase selection scheme for the optical communication systems suffering from inter-symbol-interference (ISI) distortion due to chromatic dispersion (CD) or polarization mode dispersion (PMD). In the presence of CD/PMD a proper timing phase selection is important for discrete time domain equalizers, since different timing phases produce different nonlinear ISI channels of different severity. The proposed timing phase recovery scheme based on dispersion minimization (DM) practically approximates the optimal minimum mean squared error (MMSE) timing phase without training signals which reduces overall throughput substantially, especially in time-varying channels such as PMD. The simulation results show that the proposed DM timing agrees with MMSE timing phase, under proper normalization of the received signals, for various dispersion and OSNR.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1819-1822
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• 2002

The authors propose a robust symbol timing recovery (STR) for telephone line modems supporting data rates up to 32 Mbps. The STR is initialized by a start signal from carrier sensor, and the novel method is proposed which resolves the difference between the frequency of the transmitter's clock and the receiver's clock, called baud frequency offset. The proposed method is applied on digital receiver in a 16 frequency diverse quadrature amplitude modulation (FDQAM) system.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1992.10a
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• pp.270-274
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• 1992

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• Journal of Communications and Networks
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• v.9 no.3
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• pp.265-273
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• 2007

This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.