• International Journal of Precision Engineering and Manufacturing
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• v.2 no.1
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• pp.33-42
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• 2001

In switched reluctance motor(SRM) deives, the turn-on and turn-off angles of each phase switch should be accurately controlled for accuracy and efficiency. The accuracy of the switching angles is mainly dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to implement a control algorithm of the SRM, respectively. Thus, the higher the speed of the SRM is increased, the larger the amount of the switching angle deviations are from preset turn-on and turn-off angles. Consequently, the motor can not be driven stably high speed region. There fore, a simples and low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using a simple digital logic circuit is also presented for a wide speed range operation.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1026-1029
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• 1993

Inherent speed-torque performance of Switched Reluctance Motor is similar to that of series wound DC motor. Thus, the speed of the motor is extremely regulated according to load torque. For the purpose of controlling the speed and torque of SRM it is necessary to change the applied DC link voltage or the switch-ON and switch-OFF angles which control the phase current of the motor. This paper describes speed-torque characteristics of an integral horse power Switched Reluctance Motor by adjusting the switch-ON and switch-OFF angles. Speed at rated load torque can be regulated by adjusting the switching angles and the control scheme is applied to 2kW, 3 phase, 6/4 SRM.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.296-299
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• 2003

The conventional DTC strategy provides a fast torque response even though it has very simple scheme consisted with only two hysteresis band comparators and a switching table for torque and flux control. Drawbacks of the conventional DTC are relatively high torque ripple at low speed and variation of the switching frequency according to motor speed. In this paper, the new direct torque control(DTC) schemes are proposed. Those schemes are based on the torque slope and enable to reduce the torque ripple and maintain the switching frequency constantly.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.2
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• pp.117-124
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• 2001

In a SRM drive, the on/off angles of each phase switch should be accurately controlled in order to control to torque and speed in a stable way, The accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor. However, as the speed increase, the amount of the switching angle deviation from the preset values is also increased by the sampling period of the microprocessor. Therefore, a low cost encoder suitable for a practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper. It is verified from the experiments that the proposed encoder and logic controller can be a powerful candidate a the practical low cost SRM drive.

• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.68-73
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• 2001

MPLS(Multi protocol Label Switching) is standard skill for added to speed and control the Network Traffic. MPLS concerned the routing protocol to relative Pack line, Each Pack composed label and node, saved the time to seek the address of node. MPLS worked IP, ATM and Network protocol of flame rely. MPLS is Network OSI suport model, 2Layer send to most of Packinsted of 3Layer Switching. MPLS is added speed Traffic of QoS and effective controled the Network.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.268-277
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• 2009

This paper presents an DTC-PWM (Direct Torque Control-Pulse Width Modulation) of PMSM (Permanent Magnet Synchronous Motor). The proposed DTC-PWM method combines a conventional DTC and PWM approach for switching signal generation. The actual torque is estimated by the torque estimator in conventional method, but the switching signal is generated by PWM method according to the switching rules and torque error. A effective voltage vector and zero vector are used to generate the switching signals and asymmetric switching method is applied. A simple calculation of PWM without any complex determination of space vector can assure the constant switching frequency with an constant torque and flux. The proposed torque control scheme for PMSM is verified by experimental results.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.05a
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• pp.384-387
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• 2009

There is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. Many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation (PWM) converter. Especially, the phase shift full bridge zero voltage switching PWM techniques are thought must desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.501-511
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• 1996

Typical integrated service digital network(ISDN) switching systems have several shortcomings including cumulated long call set-up delay and difficulty in higher speed packet communication. The problems come from the nature of X.25 packet swiching technique used in the systems. In this thesis, to solve the above problems, the use of frame relay service within the TDX-10 ISDN switching system is proposed and a frame handling susbsystem(FHS) is designed in order to support the high speed frame relay service in the TDX-10 switching systems. In the proposed TDX-10 architecture, the 64 Kbps packet communication can be executed more ef- ficiently and high speed packet communication is allowed. To measure theperformance characteristics of the proposed systemand to compare the performance with that of the proposed system is superior to that of the existion system and to compare the performance with that of the proposed system is superior to that of the existing system. The proposed switching system offers a seamless evolutionalry path from Narrowband-ISDNto Broadband-ISDNsince itallows anefficient channelutilization and speed packet communication.

• The KIPS Transactions:PartC
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• v.11C no.4
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• pp.527-538
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• 2004

In this paper, we present the flow aggregation method and the FLTC(flow lasting time control) algorithm to reduce the number of flows and solve the scalability problem in high speed IP switching networks. The flow aggregation based on the destination address could reduce the total number of flows, improve the label efficiency, and increase the total amount of the switched packets. The FLTC algorithm also eliminates the waste of label by deleting the flow binding efficiently. With the traces of real Internet traffics, we evaluate the performance of these schemes by simulation. The label efficiency, the average number of label used, and the percentage of packets switched and the number of packets switched are used as performance measures for this simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.