• Journal of Electrical Engineering and Technology
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• 제11권4호
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• pp.829-838
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• 2016

This paper focuses on the engineering trade-offs in designing capacitor voltage balancing schemes for modular multilevel converters (MMC) HVDC: regulation performance and switching loss. MMC is driven by the on/off switch operation of numerous submodules and the key design concern is balancing submodule capacitor voltages minimizing switching transition among submodules because it represents the voltage regulation performance and system loss. This paper first introduces the state-of-the-art MMC-HVDC submodule capacitor voltage balancing methods reported in the literatures and discusses the trade-offs in designing these methods for HVDC application. This paper further proposes a submodule capacitor balancing scheme exploiting a control signal to flexibly interchange between the on-state and the off-state submodules. The proposed scheme enables desired performance-based voltage regulation and avoids unnecessary switching transitions among submodules, consequently reducing the switching loss. The flexibility and controllability particularly fit in high-level MMC HVDC applications where the aforementioned design trade-offs become more crucial. Simulation studies for MMC HVDC are performed to demonstrate the validity and effectiveness of the proposed capacitor voltage balancing algorithm.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.271-275
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• 2001

In this paper, proposes a novel AC-DC converter of high power factor and high efficiency by partial resonant method. The input current waveform in proposed circuit is got to be a discontinuous sinusoidal form in proportion to magnitude of ac input voltage under the constant duty cycle switching. Thereupon, the input power factor is nearly unity and the control circuit is simple. Also the switching devices in a proposed circuit are operated with soft switching by the partial resonant method. The result is that the switching loss is very low and the efficiency of system is high. The partial resonant circuit makes use of a inductor using step up and $L^2SC$ (Loss-Less Snubber Condenser). The switching control technique of the converter is simplified for switches to drive in constant duty cycle. Some simulative results and experimental results are included to confirm the validity of the analytical results.

• Journal of Power Electronics
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• 제18권2호
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• 대한전기학회논문지:전력기술부문A
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• 제50권5호
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• pp.241-247
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• 2001

Network reconfiguration in distribution systems is realized by changing the status of sectionalizing switches, and is usually done for loss reduction of load balancing in the system. This paper presents an effective heuristic based switching scheme to solve the distribution feeder loss reduction problem. The proposed algorithm consists of two parts. One is to set up a decision tree to represent the various switching operations available. Another is to apply a proposed technique called cyclic best first search. the proposed algorithm identify the most effective the set of switch status configuration of distribution system for loss reduction. To demonstrate the validity of the proposed algorithm, numerical calculations are carried out the 32, 69 bus system models.

• 청정기술
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• 제21권1호
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• pp.45-52
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• 2015

본 연구에서는 양식 폐수 중 암모니아를 제거하는 전기분해 공정에 극전환을 도입하여 전극 표면에 불용성 금속화합물이 형성되는 오염 현상을 방지하고자 하였다. 한편 극전환으로 인한 전류 손실이 유리염소 이온의 생성에 미치는 영향을 파악함으로서 최적의 극전환 주기를 찾고자 하였다. 먼저 극전환 주기가 짧아지면서 전류손실로 인해 유리염소 이온의 형성 효율이 떨어지는 것을 확인하였으며 이는 암모니아 제거 효율이 감소함을 의미한다. 이에 극전환 주기에 따른 폐수 중의 칼슘과 마그네슘의 농도를 측정해 본 결과 극전환 주기를 60초 이하로 유지하면 극전환에 의한 불용성 금속화합물의 분해를 통해 전극 표면의 오염 현상을 충분한 수준에서 방지할 수 있음을 확인하였다. 따라서 높은 유리염소 이온의 생성효율 유지와 전극 오염 방지라는 두 가지 운전목적 사이에서 최적의 극전환 주기는 60초이었다.

• Journal of Power Electronics
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• 제7권3호
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• pp.181-190
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• 2007

This paper presents a novel circuit topology of a DC bus line series switch and parallel snubbing capacitor-assisted soft-switching PWM full-bridge inverter type DC-DC power converter with a high frequency planar transformer link, which is newly developed for high performance arc welding machines in industry. The proposed DC-DC power converter circuit is based upon a voltage source-fed H type full-bridge soft-switching PWM inverter with a high frequency transformer. This DC-DC power converter has a single power semiconductor switching device in series with an input DC low side rail and loss less snubbing capacitor in parallel with the inverter bridge legs. All the active power switches in the full-bridge arms and DC bus line can achieve ZCS turn-on and ZVS turn-off transition commutation. Consequently, the total switching power losses occurred at turn-off switching transition of these power semiconductor devices; IGBTs can be reduced even in higher switching frequency bands ranging from 20 kHz to 100 kHz. The switching frequency of this DC-DC power converter using IGBT power modules can be realized at 60 kHz. It is proved experimentally by power loss analysis that the more the switching frequency increases, the more the proposed DC-DC power converter can achieve a higher control response performance and size miniaturization. The practical and inherent effectiveness of the new DC-DC converter topology proposed here is actually confirmed for low voltage and large current DC-DC power supplies (32V, 300A) for TIG arc welding applications in industry.

• 전력전자학회논문지
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• 제18권4호
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• pp.312-321
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• 2013

In this paper, high efficiency control method for flyback inverter with synchronous rectifier(SR) based on photovoltaic AC modules is proposed. In this control method, the operation of SR is classified according to the voltage spike across main switch SP. When the voltage spike across SP is lower than the rating voltage of SP, the operation of active clamp circuit is interrupted for reducing the switching loss of auxiliary switch. In this time, the SR is operated for soft-switching of SP. When the voltage spike across Sp is higher than the rating voltage of SP, the operation of active circuit is activated for reducing the voltage spike. The SR is operated for reducing the conduction loss of secondary output diode. Thus, a switching loss of the main switch can be reduced in low power region, and weighted-efficiency can be improved. A theoretical analysis and the design principle of the proposed method are provided. And validity is confirmed through simulation and experimental results.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.361-364
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• 2013

기존의 DC-DC 부스트 변환기에서 사용되는 non-overlapping gate driver는 dead-time이 고정되어 있기 때문에 body-diode conduction loss 또는 charge-sharing loss가 발생하는 문제점을 가지고 있다. 이러한 손실을 줄이기 위해 사용된 기존의 적응제어 방식의 경우는 CCM 동작 시 전력트랜지스터가 동시에 on이 되는 구간이 발생하여 시스템 효율이 감소하는 문제점이 있다. 따라서 본 논문 에서는 이러한 문제점을 해결할 dead-time 적응제어 기능과 power switching 기능을 갖는 DC-DC 부스트 변환기를 설계 하였다. CMOS 0.35um 공정을 사용하였고, 2.5V 입력으로 3.3V의 출력전압을 얻으며, 스위칭 주파수는 500kHz 이다. 부하전류 150mA일 때 가장 높은 95.3%의 효율을 얻었다. 설계된 회로의 칩 면적은 $1720um{\times}1280um$이다.

• 한국전자파학회논문지
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• 제13권6호
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• pp.582-589
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• 2002

본 논문에서는 스위칭 소자인 beam lead 형태의 pin 다이오드대신에 저가인 증폭기용 HEMT를 스위칭소자로 하여 12 GHz 대역에서 동작하는 일정 삽입 손실의 5-비트 디지털 반사형 위상 변위기를 설계 및 제작한다. 기존의 이상적인 스위칭소자에 기초한 이론에 의해 설계할 때 필연적인 HEMT소자의 on, off시 큰 삽입손실차는 특정한 길이의 전송선로를 우선 스위칭 소자에 연결하여 HEMT소자의 on, off시 임피던스를 변환한 후 기존의 방식대로 설계하는 방법에 의해 제거할 쑤 있었다. 제작된 위상변위기는 설계 주파수인 12.2GHz - 12.7GHz 대역내 32단계의 스위칭 상태에서 삽입손실이 -4.5dB에서 -6dB 범위에 있으며 특히 전 단계에서 삽입 손실의 변화량이 1.5 dB 이내로 양호한 특성을 가져 본 논문에서 처음 시도한 임피던스 변환용 전송선에 의한 삽입 손실차 제거방법의 타당성을 확인할 수 있었다.

• 한국통신학회논문지
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• 제30권3A호
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• pp.178-183
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• 2005

광 버스트 교환 망에서 contention으로 인한 버스트의 손실은 망 성능에 중요한 영향을 끼친다. 많은 contention resolution 방식들이 제안되었지만 이들 중의 대부분은 contention을 방지하기 보다는 주로 수동적인 형태로 contention을 해결하는데 주력하고 있다. 본 논문에서는 망 내 트래픽 부하와 버스트 손실에 따라 버스트의 전송률을 제어하는 능동적인 contention avoidance 방식을 제안한다. 제안한 방식이, 기존의 광 버스트 전송률 제어 방식 및 버스트 전송률 제어를 제공하지 않는 일반적인 광 버스트 교환 모델과 비교하여 버스트 손실률이 향상됨과 동시에 처리율(throughput)도 보장함을, 시뮬레이션을 통해 입증한다.