• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1999년도 전력전자학술대회 논문집
• /
• pp.631-634
• /
• 1999

A new multiple-output dc-to-dc converter based on a switched capacitor circuit is proposed. The proposed converter offers multiple outputs that can be individually regulated by a direct output voltage feedback or indirect cross regulations. The performance of the new converter is demonstrated using a 10W experimental converter that delivers 5V/1A output and 3.3V/1A output from a 10∼15V input source.

• 대한전기학회논문지
• /
• 제33권12호
• /
• pp.472-479
• /
• 1984

In order to realize the simple and economic 3rd order LPF using switched-capacitor(SC), we proposed the 3rd order RC LPF using a OP amplifier and realized the 3rd order SC LPF by replacing all the resistors in the RC LPF to SC. The frequency response of SC LPF was compared with the that of RC LPF. As a result, it was found that the response of realized SC LPF is almost similar to that of RC LPF.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2013년도 전력전자학술대회 논문집
• /
• pp.315-316
• /
• 2013

This paper presents a parameter tuning method of a LLC resonant converter for a wireless charging circuit. A switched-capacitor is used to change the resonant frequency of the resonant circuit. The simulation results verify that the efficiency of the power transfer can be improved by a duty control of the switched-capacitor for various values of the coupling coefficient.

• 전자공학회논문지B
• /
• 제30B권7호
• /
• pp.42-49
• /
• 1993

In this paper, switched-capacitor building block presented which are suitable for implementation in GaAs MESFET technology. They include a current source, a gain stage, and an operational amplifier. Switched-capacitor design techniques are discussed that minimize filter sentsitivity to finite gain of the GaAs operational amplifier. Simulation results are presented on third-order elliptic lowpass ladder filter at a sampling rate of 5GHz.

• Journal of Power Electronics
• /
• 제17권5호
• /
• pp.1173-1185
• /
• 2017

In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.

• 대한전자공학회논문지SD
• /
• 제49권1호
• /
• pp.15-24
• /
• 2012

본 논문에서는 Switched-Capacitor 지연 기법의 새로운 고해상도 DPWM 발생기를 사용한 Dynamic-Response-Free SMPS를 제안한다. 제안된 회로는 Switched-Capacitor 지연 기법을 이용한 DPWM 발생기의 내부 커패시터 전압 기울기를 제어하는 방식으로 DPWM의 duty ratio를 결정한다. 제안된 회로는 컨버터의 피드백 전압과 기준전압을 비교하여 DPWM 발생기의 내부 캐패시터에 충방전되는 전류량을 제어하는 방식으로 출력전압 tracking이 가능하다. 따라서 제안된 회로는 기존 closed loop 제어 방식의 SMPS들에서 문제점이 되고 있는 동적 응답특성을 고려할 필요가 없으며, 출력 전압에 overshoot/undershoot로 인한 ringing 현상이 발생하지 않는다는 큰 장점을 가진다. 제안된 회로는 1MHz~10MHz까지 스위칭주파수를 사용자가 선택할 수 있으며, 100MHz의 내부 제어 동작 주파수로 10MHz 최대 스위칭 주파수(DPWM) 발생이 가능하다. 100MHz의 내부 제어 동작 주파수를 사용하여 10MHz 스위칭 주파수 발생시 소모되는 내부 회로의 최대 전류는 2.7mA이며, 출력 버퍼를 포함한 전체 시스템의 전류 소모는 15mA이다. 제안된 회로는 0.125%의 DPWM duty ratio 해상도를 가지고 부하에 최대 1A까지 전류공급이 가능하며, 최대 리플 전압은 8mV이다. 동부하이텍 BCD $0.35{\mu}m$ 공정 파라미터를 이용해 시뮬레이션을 수행하여 제안된 회로의 동작을 검증하였다.

• 대한전자공학회논문지
• /
• 제18권4호
• /
• pp.1-11
• /
• 1981

본 논문에서는 VIS (voltage inverter switch)를 사용한 SCF(switched capacitor filter) 설계 방법에 있어서 종래에 발표된 clocking scheme을 일반화하고, 이로써 생기는 RC, RL 등의 병렬소자들과 유손실 또는 무손실 LC 병렬공진 소자들을 제시하였다. 또 이들 업자들을 SCF의 설계에 응용함으로써 종래의 방법에 비해 연산증폭기와 Capacitor의 수를 줄일 수 있는 설계 방법에 대해 기술하였다. 이 결과로 SCF를 더욱 작은 칩(chip) 면적으로 집적화 할 수 있겠다. 또 새로운 구조를 갖는 VIS를 제시하고 이를 사명한 저역통과 여파기와 간단한 대역골지 여파기를 실험하여 그 결과가 이론치와 잘 일치함을 보였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1993년도 하계학술대회 논문집 B
• /
• pp.833-836
• /
• 1993

A flyback type power converter circuit for switched reluctance motor drives is presented. In this converter circuit, the energy extracted from an off going phase is stored in an additional capacitor. The energy stored is used to either be returned to the source frequently or energize the conducting phase during the conduction interval through the transformer. The additional switch to pass the energy stored in the capacitor to the source or the conducting phase is switched under a relatively low voltage condition. Its switching frequency is relatively high so that the size of the transformer can be reduced. The design guideline for the capacitor and the transformer is described. The effectiveness of the presented converter circuit is compared to other circuits through the analysis and experiment.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.333-336
• /
• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

• Journal of Power Electronics
• /
• 제16권5호
• /
• pp.1735-1742
• /
• 2016

This paper proposes an interleaved five-level boost converter based on a switched-capacitor network. The operating principle of the converter under the CCM mode is analyzed. A high voltage gain, low component stress, small input current ripple, and self-balancing function for the capacitor voltages in the switched-capacitor networks are achieved. In addition, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop has been researched to achieve good performances and voltage-balance effect. An experimental study has been done to verify the correctness and feasibility of the proposed converter and control strategy.