• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.631-634
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• 1999

A new multiple-output dc-to-dc converter based on a switched capacitor circuit is proposed. The proposed converter offers multiple outputs that can be individually regulated by a direct output voltage feedback or indirect cross regulations. The performance of the new converter is demonstrated using a 10W experimental converter that delivers 5V/1A output and 3.3V/1A output from a 10∼15V input source.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.12
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• pp.472-479
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• 1984

In order to realize the simple and economic 3rd order LPF using switched-capacitor(SC), we proposed the 3rd order RC LPF using a OP amplifier and realized the 3rd order SC LPF by replacing all the resistors in the RC LPF to SC. The frequency response of SC LPF was compared with the that of RC LPF. As a result, it was found that the response of realized SC LPF is almost similar to that of RC LPF.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.315-316
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• 2013

This paper presents a parameter tuning method of a LLC resonant converter for a wireless charging circuit. A switched-capacitor is used to change the resonant frequency of the resonant circuit. The simulation results verify that the efficiency of the power transfer can be improved by a duty control of the switched-capacitor for various values of the coupling coefficient.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.42-49
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• 1993

In this paper, switched-capacitor building block presented which are suitable for implementation in GaAs MESFET technology. They include a current source, a gain stage, and an operational amplifier. Switched-capacitor design techniques are discussed that minimize filter sentsitivity to finite gain of the GaAs operational amplifier. Simulation results are presented on third-order elliptic lowpass ladder filter at a sampling rate of 5GHz.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1173-1185
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• 2017

In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.1-11
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• 1981

This paper proposes a method of generalizing the clocking scheme in the Switched Capacitor Filter(SCF) design using Voltage Inverter Switches (VIS's). Parallel RC and RL elements, and parallel LC resonators can be implemented by the proposed clocking schemes Applying these new elements and the generalized clocking schemes to the SCF design, the total number of required operational amplifiers and capacitors can be reduced. Experimental results of a band- stop filter and a low-pass filter using a new type grounded VIS show good agreements with t he theoretical characteristics.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.833-836
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• 1993

A flyback type power converter circuit for switched reluctance motor drives is presented. In this converter circuit, the energy extracted from an off going phase is stored in an additional capacitor. The energy stored is used to either be returned to the source frequently or energize the conducting phase during the conduction interval through the transformer. The additional switch to pass the energy stored in the capacitor to the source or the conducting phase is switched under a relatively low voltage condition. Its switching frequency is relatively high so that the size of the transformer can be reduced. The design guideline for the capacitor and the transformer is described. The effectiveness of the presented converter circuit is compared to other circuits through the analysis and experiment.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1735-1742
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• 2016

This paper proposes an interleaved five-level boost converter based on a switched-capacitor network. The operating principle of the converter under the CCM mode is analyzed. A high voltage gain, low component stress, small input current ripple, and self-balancing function for the capacitor voltages in the switched-capacitor networks are achieved. In addition, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop has been researched to achieve good performances and voltage-balance effect. An experimental study has been done to verify the correctness and feasibility of the proposed converter and control strategy.