• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.569-577
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• 2005

In this paper, a new control scheme to use 6-switch IGBI module for 3-phase switched reluctance motors(SRM) is proposed. Compared with the conventional asymmetric bridge converter topology, it can minimize the entire system size and cost. Therefore, it may have a new topology lot SRM to compare the other ac motors, such as induction motors, brushless dc motors, and so on. The validity of the proposed method is verified by simulation, and experimental results.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.141-144
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• 1991

In this paper, we analyze the performance of ATM switch with output buffer which has a space priority control mechanism. As we assumed that the input traffic consists of loss tolerable voice and loss sensitive data, we modeled it with MMPP(Markov Modulated Poisson Process). We confirmed that the loss probability of loss sensitive traffic decreases when we use the space priority control mechanism.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.133-138
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• 2014

This paper proposes a low power-loss averaging current mode control using a resistor and bypass switch. Generally, current sensing method using a resistor has a disadvantage of power loss which degrades the efficiency of the entire systems. On the other hand, proposed measurement technique operating with bypass-switch connected in parallel with sensing resistor can reduce power loss significantly the current sensor. An analog-circuited bypass driver is implemented and used along with an average-circuit mode controller. The bypass switch bypasses the sensing current with a small amount of power loss. In this paper, a 50[W] prototype average current mode boost converter has been implemented for the experimental verification.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.309-313
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• 2001

A single-phase bi-directional inverter with a diode bridge-type resonant circuit to implement ZVT(Zero Voltage Transition) switching is proposed. It is shown that the polarized ramptime current control algorithm, a method that belongs to the family of ZACE(Zero Average Current Error) methods, is a suitable technique to integrate with a typical single-phase ZVT inverter. The proposed current control algorithm is analyzed to design the circuit with auxiliary switch which can operate with ZVT for the main power switch. The simulation results would be shown to verify the proposed current algorithm to turn the main power switch on with ZVT and to operate the inverter bi-directionally

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.441-445
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• 2009

We have developed a real-time software tool to extract a speech feature vector whose time sequences consist of three groups of vector components; the phonetic/acoustic features such as formant frequencies, the phonemic features as outputs on neural networks, and some distances of Japanese phonemes. In those features, since the phoneme distances for Japanese five vowels are applicable to express vowel articulation, we have designed a switch, a volume control and a color representation which are operated by pronouncing vowel sounds. As examples of those vowel interface, we have developed some speech training tools to display a image character or a rolling color ball and to control a cursor's movement for aurally- or vocally-handicapped children. In this paper, we introduce the functions and the principle of those systems.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.258-261
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• 2001

High Power factor Active Filter converter is used for Inverter Air conditioner power supply to meet IEC standard. In the active filter topology for power factor, extra switch just control the input current indirectly to meet the IEC standard for reducing the cost and size. In this paper, low cost converter was suggested by simulation using extra switch which auxiliary pulse is inserted and quasi resonant soft switching topology control is adapted for panel's inverter air conditioner converter Inserting auxiliary Pulse method to the extra switch has the benefit of reducing THD by low cost input control circuit. And also quasi resonant soft switching topology can reduce switching loss. So both technical is suitable for Panel's Air conditioner.

• Journal of Power Electronics
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• v.10 no.6
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• pp.702-708
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• 2010

In this paper, a fault diagnosis algorithm for brushless DC (BLDC) motor drives is proposed to maintain control performance under switch open-damage. The proposed fault diagnosis algorithm consists of a simple algorithm using measured phase current information and it detects open-circuit faults based on the operating characteristic of BLDC motors. The proposed algorithm quickly recovers control performance due to its short detection time and its reconfiguration of the system topology. It can be embedded into existing BLDC drive software as a subroutine without additional sensors. The feasibility of the proposed fault diagnosis algorithm is proven by simulation and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.391-396
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• 2009

In this paper, a control algorithm for DC-Link voltage unbalancing compensation of a four-switch inverter for a three-phase BLDC motor drive is proposed. Compared with a conventional six-switch inverter, the split source of the four-switch inverter can be obtained by splitting DC-link capacitor into two capacitors to drive the three phase BLDC motor. The voltages across each of two capacitors are not always equal in steady state because of the unbalance in the impedance of the DC-link capacitors $C_1$ and $C_2$ or the variable current flowed into the capacitor's neutral point in motor control. Despite the unbalance, if the BLDC motor may be run for a long time the voltage across one of the capacitors is more increased. So the unbalance in the capacitors voltages will be accelerated. As a result, The current ripple and torque ripple is increased due to the fluctuation of input current which flows into 3-phase BLDC motor. According to that, the vibration of motor will be increased and the whole system will be instable. This paper presents a control algorithm for DC-Link voltage unbalancing compensation. The sampling from the voltages across each of two capacitors is used to perform the voltage control of DC-Link by using the feedforward controller.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.