• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.267-270
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• 2000

In this paper, we consider the simple redundant structures with the function of hardware based active/standby control. The system includes two switch modules. The switch module is connected to a data bus, but only the active switch module has control of the data bus. The standby unit takes over the function of the active unit when the active unit failure or mode command are asserted. And this paper illustrate the high-speed router system and the overall redundant system architecture. The proposed redundant architecture for 80G Router system is verified and implemented with experiment.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.884-887
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• 2002

This paper considers a scheduling problem of routers with VOQ(Virtual Output Queue)s, where the router has an N ${\times}$N port input-queued switch and each input queue is composed of N VOQs. The objective of the paper is to develope scheduling algorithms which minimize mean tardiness under a common due date. The paper characterizes the optimal solution properties. Based upon the characterization, a integer programming is formulated for the optimal solution and two optimal solution algorithms are developed for two special cases of 2 ${\times}$2 switch and N${\times}$N switch with identical traffic.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.88-97
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• 1989

This paper proposes an efficient switch-box router which consists of two parts ; greedy poly-jog router and via minimizer. The greedy switch-box router of Luk, routes not only metal wires at horizontal tracks and poly-silicon wires at vertical tracks but also poly-siliocon wires ar horizontal tracks if necessary. The via minimizer reduces the number of vias and the wire length by fipping of each corner, parallel moving of wire segment, transformation metal into poly-silicon, and transformation poly-silicon into metal. The result is generated through the column-wise scan across the routing region. The expected time complexity is O(M(Nnet)). Where M, N, and Nnet are respectively the number of columns, rows, and nets in the routing region.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.74-81
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• 2001

In this paper. the architecture of a high-speed ATM router using ATM switch is studied and the performance of the high-speed ATM router is analyzed through simulation. The high-speed ATM router using ATM switch is able to reduce the load of router and the processing time of a packet in the router. The size of router buffers has been studied through simulation processes for the analysis of performance capacity in due course of making changes in routing time(RT), which is the performance capacity parameters of high-speed ATM routers, flow table size(FS), flow live time(FT) and input circuit efficiencies. The result of this study can be used as the source material for analyzing the suitability of equipment in upgrading networks and applying high-speed ATM routers by using ATM switches.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.244-253
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• 2005

In this paper, a performance evaluation model of the switch router with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the crossbar switch. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a network that uses the multiple buffered crossbar switches. Less than $2\%$ differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.2B
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• pp.130-137
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• 2012

In this paper, we propose core and edge router architectures with LPI(Low Power Idle) for reducing energy consumption in OBS networks. The proposed core router architecture is comprised of a BCP switch, a burst switch, line cards and sleep/wake controller for LPI. When the offered load of network is low, sleep/wake controller can change the state of the core router line card from active to sleep state for saving the energy after receiving network control packet. The edge router consists of a switch for access line card, a SCU and OBS edge router line cards. The LPI function in edge router line card is performed through network level control by network control packet, individually. Additionally, PHY/transceiver modules can transition active state to sleep state when burst assemble engine generates new bursts. To evaluate the energy saving performance of proposed architecture with LPI, the power consumption of each router is analyzed by using data sheet of commercial router and optical device. And, simulation is also performed in terms of sleep time of PHY/Transceiver through OPNET.

• The Transactions of the Korea Information Processing Society
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• v.6 no.10
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• pp.2764-2771
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• 1999

ATM has recently received much attention because of its high capacity, its bandwidth scalability, and its ability to support multiservice traffic. However, ATM is connection oriented whereas the vast majority of modern data networking protocols are connectionless. The alternative to support current service on ATM will be a router with attached switching hardware that has the ability to cache routing decisions. In this paper, we described the router using a switch and simulated the performance. From the results of the simulation, the routing delay was decreased as the number of flow channels. Cell-delay was shortest at 30,000 cell-time when the keeping time of a flow channel was. The line utilization was rapidly decrease when a flow-setup time is 20 30 cell-time. The results of this simulation could be applied to predict the performance of the router using ATM switch.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.445-448
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• 2000

This paper considers a scheduling algorithm for high-speed routers, where the router has an N x N port input-queued switch and the input queues are composed of N VOQ(Virtual Output Queue)s at each input port. The major concern of the paper is on the scheduling mechanism for the router. The paper discusses the preferred levels of the performance measures and then develope a non-linear mixed integer programming. Additionally, the paper suggests a heuristic scheduling algorithm for efficient and effective switching.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.869-872
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• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.