• Title/Summary/Keyword: Switch Function

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Optimal design and performance test of thermally controlled superconducting switch (열 제어형 초전도 스위치의 최적화 설계 및 특성 평가)

  • 고락길;배준한;권영길;조영식
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2002.02a
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    • pp.207-210
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    • 2002
  • We had designed thermally controlled superconducting switches using a general nonlinear optimized algorithm with constraints and tested its performance. Objective function was to minimize the total volume of the superconducting switch. And constraints were to have designed resistance in normal status and temperature. In order to compare performance of the optimized superconducting switch, we made another one which had geometrically different parameters but had same structure and resistance value when the superconductor part is normal status by heater. Objective function converged very rapidly. As result, volume of the adiabatic part and total volume of the switch were reduced to more than 70% and 30% respectively. Also, even if same heater power was supplied with NiCr wire heater, the optimized superconducting switch had very fast On-OFF switching performance comparing with unoptimized switch.

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Implementation of High Speed Router's Redundancy Architecture (고속 네트워크 시스템의 이중화 회로 구현)

  • 강덕기;이상우;이준철;이형섭;이영천
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.267-270
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    • 2000
  • In this paper, we consider the simple redundant structures with the function of hardware based active/standby control. The system includes two switch modules. The switch module is connected to a data bus, but only the active switch module has control of the data bus. The standby unit takes over the function of the active unit when the active unit failure or mode command are asserted. And this paper illustrate the high-speed router system and the overall redundant system architecture. The proposed redundant architecture for 80G Router system is verified and implemented with experiment.

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The Development of ASS Controller Using DSP (DSP를 이용한 자동고장구분개폐기의 제어장치 개발)

  • Woo, Chun-Hee;Han, Tae-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.53 no.3
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    • pp.142-147
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    • 2004
  • In this study, We developed the microprocessor based controller for Auto Section Switch(ASS). This is installed at consumer's medium-high voltage(load capacity is below 4,000 kVA) switchgear. This function is cooperate with protection device of fault section and automatically dividing the section. And It is designed by Air putter type extinction structure and adopt the mechanism and breaking part module of existing Load Breaker Switch. In addition, We successfully conducted the operation test and checked main function of proto-type.

A Study on the Analysis and Prediction of switch currents in PWM inverters (PWM 인버터에서 스위치 전류의 해석과 그 예측에 관한 연구)

  • Ji, Ho-Chul;Jeong, Seung-Gi
    • Proceedings of the KIEE Conference
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    • 1997.11a
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    • pp.448-452
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    • 1997
  • Theoretical average current and rms current equations are solved using the analytical method in the 3phase voltage-fed inverter. Experimental switch current equations are established by simulation and compared with theoretical equations. As a result of analysis, average and rms currents of switch devices are represented by a function as power factor and modulation index. Especially, equations of this paper are represented as a function of a single factor(K) equal to the product of the power factor and modulation index. Method that can find current levels of switch devices for inverter design and conduction loss of inverter in a simple and accurate manner is presented. Influences of modulation method on switch current are also studied.

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Direct Power Control without Current Sensors for Nine-Switch Inverters

  • Pan, Lei;Zhang, Junru;Wang, Kai;Wang, Beibei;Pang, Yi;Zhu, Lin
    • Journal of Power Electronics
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    • v.18 no.1
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    • pp.1-10
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    • 2018
  • Recently, the nine-switch inverter has been proposed as a dual output inverter. To date, studies on the control strategies for NSIs have been mostly combined with their application. However, in this paper, a mathematical model and control strategy for nine-switch inverters has been proposed in view of the topology. A switching function model and equivalent circuit model of a nine-switch inverter have been built in ${\alpha}{\beta}$ coordinates. Then, a novel current observer with an improved integrator is proposed based on the switching function model, and a direct power control strategy is proposed. No current sensors are used in the proposed strategy, and only two voltage sensors are employed. The performance of the proposed control method is verified by simulation and experimental results.

A Study for Improving Performance of ATM Multicast Switch (ATM 멀티캐스트 스위치의 성능 향상을 위한 연구)

  • 이일영;조양현;오영환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.12A
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    • pp.1922-1931
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    • 1999
  • A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.

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Plant Light Signaling Mediated by Phytochromes and Plant Biotechnology

  • Song, Pill-Soon
    • Proceedings of the Botanical Society of Korea Conference
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    • 1998.07a
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    • pp.83-96
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    • 1998
  • The plant pigment proteins phytochromes are a molecular light sensor or switch for photomorphogenesis involving a variety of growth and developmental responses of plants to red and far-red wavelength light. Underscoring the photomorphogenesis mediated by phytochromes is the light signal transduction at molecular and cellular levels. For example, a number of genes activated by the phytochrome-mediated signal transduction cascade have been identified and characterized, especially in Arabidopsis thaliana. The light sensor/switch function of phytochromes are based on photochromism of the covalently linked tetrapyrrole chromophore between the two photoreversible forms, Pr and Pfr. The photochromism of phytochromes involves photoisomerization of the tetrapyrrole chromophore. The "photosensor" Pr-form ("switch off" conformation) of phytochromes strongly absorbs 660 nm red light, whereas the "switch on" Pfr-conformation preferentially absorbs 730 nm far-red light. The latter is generally considered to be responsible for eliciting transduction cascades of the red light signal for various responses of plants to red light including positive or negative expression of light-responsive genes in plant nuclei and chloroplasts. In this paper, we discuss the structure-function of phytochromes in plant growth and development, with a few examples of biotechnological implications.

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Structure and Implementation of Fully Interconnected ATM Switch (Part II : About the implementation of ASIC for Switching Element and Interconnected Network of Switch) (완전 결합형 ATM 스위치 구조 및 구현 (II부 스위치 엘리먼트 ASIC화 및 스위치 네트워크 구현에 대하여))

  • 김경수;김근배;박영호;김협종
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.1
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    • pp.131-143
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    • 1996
  • In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.

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Performance evaluation of fully-interconnected ATM switch (part II: for bursty traffic andnonuniform distribution) (완전 결합형 ATM 스위치의 성능분석 (II부 : 버스티 트래픽 및 비균일 분포에 대하여))

  • 전용희;박정숙;정태수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.8
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    • pp.1926-1940
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    • 1998
  • This paper is the part II of research results on the performance evaluation of fully interconnected ATM switch, and includes the performance evaluation results for bursty traffic and nonuniform distribution. The switch model is a fyully interconnected switch type proposed by ETRI and is the proper architecutre for a small-sized switch element. The proposed switch consists of two steps of buffering scheme in the switch fabric in order to effectively absorb the effect of bursty nature of ATM traffic. The switch uses bit addressing method for addressing shcmeme and thus it is easy to implement multicasting function without adding additional functional block. In order to incorporate the bursty nature of traffic in ATM networks, we use IBP(Interrupted Bernoulli Process) model as an input traffic model as well as random traffic model which has been used as a traditional traffic model. In order to design the various scenarios for simulation, we considered both uniform and nonuniform output distribution, and also implemented multicast function. In this paper, we presented the simulation results in diverse environments and evaluated the performance of the switch.

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Ethernet-Based Avionic Databus and Time-Space Partition Switch Design

  • Li, Jian;Yao, Jianguo;Huang, Dongshan
    • Journal of Communications and Networks
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    • v.17 no.3
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    • pp.286-295
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    • 2015
  • Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.