• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1148-1159
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• 1997

In the broadband integrated service digital networks (B-ISDN), ATM switches hould be abld to accommodate diverse types of applications ith different traffic characteristics and quality ddo services (QOS). Thus, in order to increase the utilization of switches and satisfy the QOS's of each traffic type, some types of priority control schemes are needed in ATM switches. In this paper, a nonblocking input and output queueing ATm switch with capacity C is considered in which two classes of traffics with different loss probability constraints are admitted. 'Partial push-out' algorithm is suggested as a loss priority control schemes, and the performance of this algorithm is analyzed when this is adopted in input buffers of the switch. The quque length distribution of input buffers and loss probabilities of each traffic are obtained using a matrix-geometric solution method. Numerical analysis and simulation indicate that the utilization of the switch with partial push-out algorithm satisfying the QOS's of each traffic is much higher than that of the switch without control. Also, the required buffer size is reduced while satisfying the same QOS's.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• Journal of Internet Computing and Services
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• v.9 no.2
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• pp.15-23
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• 2008

This paper proposes the new structural MOQ(Multiple Input/Output-Queued) switch which guarantees QoS while maintaining high efficiency and deals with the Anti-Empty algorithm which is new arbitration algorithm to be used for the proposed switch. The new structure of the proposed switch based on MIQ, MOQ is designed to have the same buffer speed as the external line speed. Also, the proposed switch makes it possible to remove the weak point of existing methods and introduces the new method of the MOQ operation to support QoS. Therefore, this switch is equal to the Output Queued switch in efficiency and delay, and guarantees the high-speed switching supporting QoS without cell loss.

• Journal of KIISE:Information Networking
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• v.30 no.3
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• pp.416-423
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• 2003

This paper proposes a continuous-time queuing model of a shared-buffer packet switch and an approximate algorithm. N arrival processes have heterogeneous busty traffic characteristics. The arrival processes are modeled by Coxian distribution with order 2 that is equivalent to Interruped Poisson Process. The service time is modeled by Erlang distribution with r stages. First the approximate algorithm performs the aggregation of N arrival processes as a single state variable. Next the algorithm discompose the queuing system into N subsystems which are represented by aggregated state variables. And the balance equations based on these aggregated state variables are solved for by iterative method. Finally the algorithm is validated by comparing the results with those of simulation.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.630-632
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• 1998

본 논문에서는, Multi[le-Buffered a$\times$a Crossbar 수위치의 성능 분석 모형을 제안하고 스위치에 장착된 buffer 의 개수의 중가에 다른 성능 향상 추이를 분석하였다. buffered스위치 기법은 다수 데이터 패킷을 동시에 전송할 때 네트웍에서 발생되는 충돌문제를 효과적으로 해결할 수 있는 방법으로 널리 알려져있다. 제안된 성능 예측 모형은 스위치 입력 단에 유입되는 데이터 패킷이 buffered 스위치 내부에서 전송되는 유형을 확률적으로 분석하여 수립되었다. 모형의 수학적 복잡도 해결을 위하여 확률 식 유도 과정 등에 steady state 개념을 도입하였다. 제안한 모형은 스위치 크기 및 스위치에 장착된 buffer의 개수와 무관하게 buffered a$\times$a 크로스바 스위치의 성능 예측을 가능케 하고, 나아가서 이들로 구성된 다층 연결 망의 성능 분석에 확대 적용이 가능하다. 제안한 수학적 성능 분석 연구는 실효성 검증을 위하여 병행된 시뮬레이션 결과는 미세한 오차 범위 내에서 모형의 예측 데이터와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다. 또한, 분석 결과 스위치에 소수의 버퍼를 장착했을 때, throughput이 크게 증가하지만, 네 개 이상의 버퍼를 장착되는 버퍼의 개수가 네 개 정도일 경우 가격 대 성능비가 우수한 것으로 추론되었다.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.68-75
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• 1998

The Asynchronous Transfer Mode(ATM) networks are being adopted as backbones over various parts of Internet. Also, TCP is one of the most widespread transport protocols, nowadays. It can be used with ATM. But, TCP shows poor end-to-end performance on ATM networks. Effective throughput of TCP over ATM can be quite low when cells are dropped at the congested ATM switch. The low throughput is due to wasted bandwidth as congested link transmits cells from corrupted packets. This paper examines the behavior of TCP over ATM-UBR using EPD switch in a broadband environment. With a threshold close to the buffer size, the buffer can be used more efficiently, but more drops and retransmission occurs. If the threshold is much less than buffer size, efficient is not good, but few drops can happen. Therefore, decision of the threshold is important.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.25-32
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• 2011

NoC is actively being studied recently in order to overcome the limitations of shared-bus architecture. We proposed an NoC architecture which employs a buffer that plays a similar role of a proxy server in a computer network to enhance the communication efficiency of NoC architecture. In the proposed NoC architecture, whenever the master has a difficulty in communicating with the slave directly, the master communicates with the proxy server which is able to communicate with the slave on behalf of the master. With the proposed scheme in NoC, we can increase the speed and the bandwidth of communication channel. The experimental results showed that overall communication efficiency was significantly improved by sending the packets to the proxy server rather than holding them in the switch buffer.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.73-80
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• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1910-1916
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• 1999

This paper suggested to solve ATM switch performance and service rate which was input buffer managed scheme in ATM network with burst traffic characteristics, For this purpose, ATM multiplexer is prepared before sending for handling burst random input traffic to multiplex and then sort based on cell inter-arrival time and cell processing due time which had been marked after that. The server looks for cell header with the most shortest due time and sends it, thus it is satisfied that real time traffic for instance CBR and rt-VBR was guaranteed cell processing time to send fast than non real time traffic. For analysis of ATM switch performance with cell processing due time and priority, each output port has divided into four different virtual buffer and each buffer has assigned different cell inter-arrival time and processing due time according to ATM Forum for example CBT/rt-VBR, nrt-VBR, ABR and UBR and showed it’s optimal service parameters then analyzed service rate behaviors according to each traffic characteristics.