• Title/Summary/Keyword: Surface Mount

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Simulator of Accuracy Prediction for Developing Machine Structures (기계장비의 구조 특성 예측 시뮬레이터)

  • Lee, Chan-Hong;Ha, Tae-Ho;Lee, Jae-Hak;Kim, Yang-Jin
    • Journal of the Korean Society for Precision Engineering
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    • v.28 no.3
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    • pp.265-274
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    • 2011
  • This paper presents current state of the prediction simulator of structural characteristics of machinery equipment accuracy. Developed accuracy prediction simulator proceeds and estimates the structural analysis between the designer and simulator through the internet for convenience of designer. 3D CAD model which is input to the accuracy prediction simulator would simplified by the process of removing the small hole, fillet and chamfer. And the structural surface joints would be presented as the spring elements and damping elements for the structural analysis. The structural analysis of machinery equipment joints, containing rotary motion unit, linear motion unit, mounting device and bolted joint, are presented using Finite Element Method and their experiment. Finally, a general method is presented to tune the static stiffness at a rotation joint considering the whole machinery equipment system by interactive use of Finite Element Method and static load experiment.

Research of Optimum Reflow Process Condition for 0402 Electric Parts (0402칩의 무연솔더링 최적공정 연구)

  • Bang, Jung-Hwan;Lee, Se-Hyung;Shin, Yue-Seon;Kim, Jeong-Han;Lee, Chang-Woo
    • Journal of Welding and Joining
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    • v.27 no.1
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    • pp.85-89
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    • 2009
  • Reflow process conditions were investigated for 0402 electric parts with Sn-3.0Ag-0.5Cu solders. Circle hole shape metal mask with 100 m thickness showed excellent printability. Self alignment abilities were 71% for 1005 chips, 52% for 0603 chips, and 3% for 0402 chips. Average joining strengos were 1990 gf for 1005 chips, 867 gf for 0603 chips, and 525 gf for 0402 chips. As mis-mounting angle increased, joining strength decreased. Considering self-alignment ability, mounting angle had to be under $5^{\circ}$ and contact area of the chips had to be over 40% for Pb-free soldering process for 0402 chips.

In situ synthesis of acrylic emulsion for improvement of anti corrosion property on steel plate (금속 코팅용 아크릴 올리고머 에멀젼의 합성에 관한 연구)

  • Lee, Soo;Park, Keun-Ho;Jin, Seok-Hwan;Park, Shin-Kyu
    • Journal of the Korean Applied Science and Technology
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    • v.25 no.4
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    • pp.485-494
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    • 2008
  • The acrylic coating emulsions were prepared by the emulsion polymerization to protect the surface of steel plate from the corrosion chemicals like acid, base and salt water. MMA(methyl methacrylate), styrene, BA(butyl acrylate), and 2-HEMA(2-hydroxyethyl methacrylate) were used as monomer. KPS(potassium persulfate) and SBS(sodium bisulfite) as redox initiator and SDBS(sodium dodecylbenzene sulfonate) as emulsifier were used on the emulsion polymerization reaction. The most stable in-situ coating was obtained when 10% of MMA was added. Both particle size and quantity in emulsion were decreased as increasing the mount of SDBS. the most stable prepared coating emulsion with polyisocyanate crosslinker showed very high anticorrosion properties on the coated steel layer to salt water, whereas no significant improvement of anticorrosion property to acdic and basic condition it showed.

Investigation of Asymmetric Aspherical Triangular Prism Optical System for Video Information Display (영상정보디스플레이용 비대칭 비구면 삼각 프리즘 광학계 연구)

  • Youn, Gap-Suck;Yoo, Kyung-Sun;Hyun, Dong-Hoon
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.23 no.6
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    • pp.590-595
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    • 2014
  • We have investigated anamorphic prism lenses with distortions of 0.3-0.5%. We designed the plastic triangular lens and confirmed the minimum resolution using MTF graphs. Also we confirmed that the SVGA optical system can realize a resolution of $864{\times}648$ 56 megapixels. A distortion of about 0.5% aberration appears in the maximum field, and a finite beam aberration of about $15{\mu}m$ is confirmed. We made a mold based on the design data and completed the prism lens through exodus molding. We confirmed the shape error (< $30{\mu}m$) and surface roughness (> 40 nm) of the three sides. We made the video-information-display prototype glasses using prism lens by measuring the performance, we determined the distortion aberration (0.3%) and SVGA resolution. Our approach will enable fabrication of a portable large-screen display device for glasses and sunglasses for the domestic market and, after 2015, for the world market.

A prediction of the thermal fatigue life of solder joint in IC package for surface mount (표면실장용 IC 패키지 솔더접합부의 열피로 수명 예측)

  • 윤준호;신영의
    • Journal of Welding and Joining
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    • v.16 no.4
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    • pp.92-97
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    • 1998
  • Because of the low melting temperature of solder, each temperature cycle initiates an irrecoverable creep deformation at the solder interconnection which connects the package body with the PCB. The crack starts and propagates from the position where the creep deformation is maximized. This work has tried to compare and analyze the thermal fatigue life of solder interconnection which is affected by the lead material, the size of die pad, chip thickness, and interface delamination of 48-Pin TSOP under the temperature cycle ($0^{\circ}C$~1$25^{\circ}C$). The crack initiation position and thermal fatigue life which are calculated by using FEA method are well matched with the results of experiments. The thermal Fatigue life of copper lead frame is extended around 3.6 times longer than that of alloy 42 lead frame. It is maximized when the chip size is matched with the length of the lead. It tends to be extended as the thickness of chip got thinner. As the interfacial delamination between die pad and EMC is increased, the thermal fatigue life tends to decrease in the beginning of delamination, and increase after the delamination grew after 45% of the length of die pad.

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Unified Approach to Path Planning Algorithm for SMT Inspection Machines Considering Inspection Delay Time (검사지연시간을 고려한 SMT 검사기의 통합적 경로 계획 알고리즘)

  • Lee, Chul-Hee;Park, Tae-Hyoung
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.8
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    • pp.788-793
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    • 2015
  • This paper proposes a path planning algorithm to reduce the inspection time of AOI (Automatic Optical Inspection) machines for SMT (Surface Mount Technology) in-line system. Since the field-of-view of the camera attached at the machine is much less than the entire inspection region of board, the inspection region should be clustered to many groups. The image acquisition time depends on the number of groups, and camera moving time depends on the sequence of visiting the groups. The acquired image is processed while the camera moves to the next position, but it may be delayed if the group includes many components to be inspected. The inspection delay has influence on the overall job time of the machine. In this paper, we newly considers the inspection delay time for path planning of the inspection machine. The unified approach using genetic algorithm is applied to generates the groups and visiting sequence simultaneously. The chromosome, crossover operator, and mutation operator is proposed to develop the genetic algorithm. The experimental results are presented to verify the usefulness of the proposed method.

BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.04a
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    • pp.27-34
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    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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THE NEW THICK-FILM HYBRID CONVERTERS FOR HALOGEN AND FLUORESCENT LAMPS

  • Gondek, J.;Dzialek, K.;Kocol, J.;Kawa, B.
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.04a
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    • pp.57-65
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    • 2001
  • Economical consumption of energy, longer life of lamps, higher lighting comfort and new aesthetic of illumination is subject of numerous research and development works. The halogen lamps are an example of positive solution some of above mentioned problems. The electronic transformers are more frequent used for their supply. In comparison with conventional transformers they have less weight, less volume and 60% less power tosses. Their advantages are particular visible, when the hybrid technique is applied. The paper presents the results of engineering research and development works carried out ill Private Institute of Electronic Engineering, in R. & D. Center for Hybrid Microelectronics and Resistors and in Technical School of Communications in Krakow, in the field of the design and exploitation tests of hybrid converters 220V AC /12V DC (electronic transformers) and electronic ballasts destined for the supply of halogen lamps 20W to 150W and fluorescent lamps respectively. To perform the converters, thick film technology and surface mount technology were used. For the protection of converter electronic circuit the thick film temperature sensor and transistors were applied. Moreover the paper presents the base application circuits of elaborated converters, their technical parameters and exploitation results. The development perspectives of hybrid domain of hybrid circuits are also discussed.

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QFN Solder Defect Detection Using Convolutional Neural Networks with Color Input Images (컬러 입력 영상을 갖는 Convolutional Neural Networks를 이용한 QFN 납땜 불량 검출)

  • Kim, Ho-Joong;Cho, Tai-Hoon
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.3
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    • pp.18-23
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    • 2016
  • QFN (Quad Flat No-leads Package) is one of the SMD (Surface Mount Device). Since there is no lead in QFN, there are many defects on solder. Therefore, we propose an efficient mechanism for QFN solder defect detection at this paper. For this, we employ Convolutional Neural Network (CNN) of the Machine Learning algorithm. QFN solder's color multi-layer images are used to train CNN. Since these images are 3-channel color images, they have a problem with applying to CNN. To solve this problem, we used each 1-channel grayscale image (Red, Green, Blue) that was separated from 3-channel color images. We were able to detect QFN solder defects by using this CNN. In this paper, it is shown that the CNN is superior to the conventional multi-layer neural networks in detecting QFN solder defects. Later, further research is needed to detect other QFN.

Design and Manufacture of Multi-layer VCO by LTCC (저온 동시소성 세라믹을 이용한 적층형 VCO의 설계 및 제작)

  • Park, Gwi-Nam;Lee, Heon-Yong;Kim, Ji-Gyun;Song, Jin-Hyung;Rhie, Dong-Hee
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05c
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    • pp.291-294
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    • 2003
  • The circuit substrate was made from the Low Temperature Cofired Ceramics(LTCC) that a $\varepsilon_\gamma$ was 7.8. Accumulated Varactor and the low noise transistor which were a Surface Mount Device-type element on LTCC substrate. Let passive element composed R, L, C with strip-line of three dimension in the multilayer substrate circuit inside, and one structure accumulate band-pass filter, resonator, a bias line, a matching circuit, and made it. Used Screen-Print process, and made Strip-line resonator. A design produced and multilayer-type VCO(Voltage Controlled Oscillator), and recognized a characteristic with the Spectrum Analyzer which was measurement equipment. Measured multilayer structure VCO is oscillation frequency 1292[MHz], oscillation output -28.38[dBm], hamonics characteristic -45[dBc] in control voltage 1.5[V], A phase noise is -68.22[dBc/Hz] in 100 KHz offset frequency. The oscillation frequency variable characteristic showed 30[MHz/V] characteristic, and consumption electric current is approximately 10[mA].

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