• ETRI Journal
• /
• v.19 no.4
• /
• pp.402-413
• /
• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• 한국초전도학회:학술대회논문집
• /
• v.16
• /
• pp.48-48
• /
• 2006

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.2
• /
• pp.97-101
• /
• 2003

New Pt/Ti and hi/Ti double-metal structures have been investigated for the application of a diffusion barrier between Cu and Si in deep submicron integrated circuits. Pt/Ti and Ni/Ti were deposited using E-beam evaporator at room temperature. The performance of Pt/Ti and Ni/Ti structures as diffusion barrier against Cu diffusion was examined by charge pumping method, gate leakage current, junction leakage current, and SIMS(secondary ion mass spectroscopy). These evaluation indicated that Pt/Ti(200${\AA}$/100${\AA}$) film is a good barrier against Cu diffusion up to 450$^{\circ}C$.

• Electrical & Electronic Materials
• /
• v.8 no.6
• /
• pp.708-714
• /
• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.1
• /
• pp.7-13
• /
• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• Progress in Superconductivity
• /
• v.7 no.1
• /
• pp.6-10
• /
• 2005

We have studied feasibility of single-layer second-order $high-T_c$ SQUID gradiometers in magnetocardiography. We have measured human cardiomagnetic signals using a short-baseline (5.8 mm) single-layer second-order YBCO gradiometer in partially shielded environments. The gradiometer has an overall size of $17.6\;mm{\times}6\;mm$ and contains three parallel-connected pickup coils which are directly coupled to a step-edge junction SQUID. The gradiometer showed an unshielded gradient noise of $0.84\;pT/cm^2/Hz^{1/2}$ at 1 Hz, which corresponds to an equivalent field noise of $280\;fT/Hz^{1/2}$. The balancing factor was $10^3$. Based on the same design rules as the short-baseline devices, we have studied fabrication of 30 mm-long baseline gradiometers. The devices had an overall size of $70.2\;mm{\times}10.6\;mm$ with each pickup coil of $10\;mm{\times}10\;mm$ in outer size. As Josephson elements we made two types of submicron bridges, which are variable thickness bridge (VTB) and constant thickness bridge (CTB), from $3\;{\mu}m-wide$ and 300 nm-thick YBCO lines with a thin layer of Au on top by using a focused ion beam (FIB) patterning method. VTB was 300 nm wide, 200 nm thick, 30 nm long with Au removed and CTB 100 nm wide and 30 nm long. In temperature-dependent critical currents, $I_c(T)$, VTB showed an nonmetallic barrier-type behavior and CTB an SNS behavior. We believe that those characteristics are ascribed to naturally formed grain boundaries crossing the bridges.

• Transactions on Electrical and Electronic Materials
• /
• v.5 no.5
• /
• pp.169-172
• /
• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.