• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.382-385
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• 2003

Introduction of digital broadcasting service does not only mean the change of information transmission method but also the change of total broadcasting system. In past day, Television was only received one-sided information from broadcasting station, but digital broadcasting means that digital television becomes the most important means of information transmission by the introduction of new programming, lots of channels, data service, multi communication. In the age of the digital broadcasting, the recording and replay medium's interest is getting higher. The medium is able to record more than 24 hours' digital broadcasting programs without additional tapes. In this paper the recording and replay device using HDD was implemented and device driver based on linux was programmed. It has Intel PXA250 processor and hard disk is used as storage equipment. And transport Stream is saved on hard disk through PXA250's data bus. FIFO is added to solve the different saving speed and FPGA is also added to display the saved data.

• The Journal of the Acoustical Society of Korea
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• v.20 no.7
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• pp.63-68
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• 2001

This paper describes the details of ITU-T SGIS G.729A speech coder implementation using ARM9 Thumb/sup R/ processor core and various techniques used in the optimization process. ITU-T G.729 speech coder is the standard of the toll quality 8 kbit/s speech coding. The input to the speech encoder is assumed to be a 16 bits PCM signal at a sampling rate of 8000 samples per second. G.729A is reduced complexity version of the G.729 coder. This version is bit stream interoperable with the full version. The implemented coder requires 34.8 MIPS for the encoder and 8.1 MIPS for the decoder, 36.5 kBytes of program ROM and 6.3 kBytes of data RAM, respectively. The implemented coder is tested against the set of 9 test vectors provided by ITU-T for bit exact implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2031-2041
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• 1999

In this paper, we present the HVIS (Hybrid Video Information System) which bolsters up meaning retrieval of all the various users by integrating feature-based retrieval and annotation-based retrieval of unformatted formed and massive video data. HVIS divides a set of video into video document, sequence, scene and object to model the metadata and suggests the Two layered Hybrid Object-oriented Metadata Model(THOMM) which is composed of raw-data layer for physical video stream, metadata layer to support annotation-based retrieval, content-based retrieval, and similarity retrieval. Grounded on this model, we presents the video query language which make the annotation-based query, content-based query and similar query possible and Video Query Processor to process the query and query processing algorithm. Specially, We present the similarity expression to appear degree of similarity which considers interesting of user. The proposed system is implemented with Visual C++, ActiveX and ORACLE.

• Korean Chemical Engineering Research
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• v.51 no.4
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• pp.455-459
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• 2013

The fuel processor for the portable fuel cell includes multi-step processes consisting of hydrogen generator, heat generator and several CO clean-up stages. One of requirements of the fuel processor for portable fuel cell system is a rapid start-up time. Especially, the warm-up time for WGS reactor is crucial factors for total start-up time. In this paper, active heating protocol, which is the heating protocol of WGS reactor supplied by the oxidation of CO rich reformate in the initial stage, is used for a rapid start-up. The air stream fed to the inlet of WGS reactor rapidly oxidize the CO rich reformate in the WGS reactor. Therefore, CO concentration in reformate quickly stabilized at the desired concentration without CO surges.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of KIISE:Databases
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• v.33 no.6
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• pp.563-577
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• 2006

A stream processor uses resource sharing method for efficient of limited resource in multiple continuous queries. The previous methods process aggregate queries to consist the level structure. So insert operation needs to reconstruct cost of the level structure. Also a search operation needs to search cost of aggregation information in each size of sliding windows. Therefore this paper uses linear structure for optimization of sliding window aggregations. The method comprises of making decision, generation and deletion of panes in sequence. The decision phase determines optimum pane size for holding accurate aggregate information. The generation phase stores aggregate information of data per pane from stream buffer. At the deletion phase, panes are deleted that are no longer used. The proposed method uses resources less than the method where level structures were used as data structures as it uses linear data format. The input cost of aggregate information is saved by calculating only pane size of data though numerous stream data is arrived, and the search cost of aggregate information is also saved by linear searching though those sliding window size is different each other. In experiment, the proposed method has low usage of memory and the speed of query processing is increased.

• Journal of KIISE:Databases
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• v.37 no.5
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• pp.275-284
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• 2010

GPUs are stream processors based on multi-cores, which can process large data with a high speed and a large memory bandwidth. Furthermore, GPUs are less expensive than multi-core CPUs. Recently, usage of GPUs in general purpose computing has been wide spread. The CUDA architecture from Nvidia is one of efforts to help developers use GPUs in their application domains. In this paper, we propose techniques to parallelize a skyline algorithm which uses a simple nested loop structure. In order to employ the CUDA programming model, we apply our optimization techniques to make our skyline algorithm fit into the performance restrictions of the CUDA architecture. According to our experimental results, we improve the original skyline algorithm by 80% with our optimization techniques.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.