• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.19-37
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• 1996

Scanning electron microscopy (SEM) has been applied to observe directly the {{{{ SQRT { 19} }}}}${\times}${{{{ SQRT { 19} }}}} and (1${\times}$1)HT reconstructions and the transition associated step bunching on the GaAs (111)B surfaces under As pressure. Close to the transition point, {{{{ SQRT { 19} }}}}${\times}${{{{ SQRT { 19} }}}}an d (1${\times}$1)HT reconstructions are observed in dark and bright domains by SEM and determined by micro-probe reflection high-energy electron diffraction (${\mu}$-RHEED). The reconstruction diagram shows hyster-esis. The stepped surface morphology during the reconstruction transition was unstable. Heavy step bunching with rough macrostep edges was observed.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.220-220
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• 2008

• Proceedings of the Korean Vacuum Society Conference
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• 2005.08a
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• pp.50-50
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• 2005

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.189-189
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• 1999

초미세 전자 소자에 대한 개발에 대한 요구는 최근 들어 원자 단위의 구조물 제작에 대한 연구로까지 나아 가게 하고 있다. 좋은 물리적 성장을 가지는 양자도선(quantum wire), quantum dot와 같은 nano 단위 구조물 제작에 대한 요구는 그 가능성의 하나로 , 기울어진 vicinal) 표면위에서의 박막 성장에 대한 연구로 이어지고 있다. 기울어진 표면은 한 원자층으로 된 많은 계단들을 가지고 있는 표면이고, 이러한 계단들의 존재는 박막 성장 시 흡착 원자가 계단 끝에 부착될 확률을 증가 시켜, stepflow 성장과 같은 준 층별 성장을 만들 가능성을 높여주며, sub-ML증착에 대해서 원자가 계단면을 따라 길게 늘어선 양자도선과 같은 성장이 가능한 표면이라는 점에서 관심을 갖게 한다. 그러나 최근의 연구들에 의하면 기울어진 표면 위에서의 성장도 Schwoebel 장벽과 같은 분산 장벽의 존재로 계단과 수직인 축 방향으로 거친 모양의 island가 형성되는 Bails-Zangwill 불안정성이 나타나는 것으로 보고되고 있고, 이것은 준 층별 성장이나 양자 도선과 같은 성장을 방해하는 것으로 알려져 있다. 이러한 불안정성을 해결할 가능성으로 최근 들어 한 계단의 높이가 큰 step bunching 이 생겨난 표면위에서의 성장이 제기 되고 있으나, 아직 확인되지 않았다. 본 연구는 이러한 기울어진 표면 위에서 박막을 성장 할 때 층흐름(step flow) 성장이 가능한 역학적 동역학적 조건을 구하고자 하며, 방법으로는 KMC 시뮬레이션을 이용한다. 단원자로 구성된 계단이 있는 기울어진 표면 위에서의 homoepitaxy의 경우, 성장 양식은 계단과 계단 사이의 테라스 간격에 크게 의존한다. 테라스 간격이 좁을수록 성장은 보다 층흐름 성장에 근접한다. 그러나 다층으로 성장시킨 시뮬레이션의 결과는 일반적인 장벽 조건 아래에서는 계단의 방향과 수직인 방향으로 평평한 면에서와 동일한 크기를 가지는 island가 성장하는 것을 볼 수 있고, 이 것은 Bails-Zangwill 불안정성이다. 그러나 계단 사이의 테라스 간격이 매우 좁은 경우 5-6ML 성장 이하에서는 층흐름 성장과 동일한 성장이 이루어지나 계단을 따라서 미소한 크기의 거칠기가 나타난다. 동일한 기울어진 경사면에 대해서는 분산속도가 좋을수록 보다 계단 면을 따라 보다 큰 크기의 island가 나타난다. 분산 장벽과 같이 동역학적인 요소만으로는 완벽한 층흐름 성장은 높은 온도, 극히 낮은 분산 장벽이라는 조건 이외에는 얻기 어렵다. 그리고 층흐름 성장의 가능성으로 제시된 step bunching 일 일어난 다층 높이의 계단을 가진 면도 다층의 수만큼 계단수를 늘려주는 것과 동일한 결과가 나타나며, 이 경우도 층흐름 성장에는 근접하지만 완전한 형태의 성장은 얻기는 역시 어렵다. 따라서 원자단위의 도선이나 층흐름 성장은 계단과 계단 사이의 인력 또는 척력과 같은 역학적인 요소를 고려할 때 만이 가능할 것으로 보인다.

• Korean Journal of Metals and Materials
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• v.47 no.1
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• pp.32-37
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• 2009

Molecular dynamic simulations on the structural evolution of the Si(001) vicinal surfaces, which are tilted with respect to [100] and [110] directions were performed by using the empirical Tersoff potential. Tersoff potential was implemented at LAMMPS code and confirmed to describe the properties of Si. When the steps are generated along [100] direction, symmetric dimer rows formed with respect to the step edges. On the other hand, when the steps are generated along [110] direction, alternating dimer rows form with respect to the step edges. The configurational differences between the two vicinal surfaces were discussed in terms of the surface diffusion and the possibility of preventing step bunching for the (001) vicinal surface tilted along [100] direction was suggested.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.85-85
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• 2000

Stranski-Krastanow 자발형성 방법에 의한 양자점의 성장은 다른 공정에 비해 결함이 적은 반면에 크기와 위치를 조절하기 어렵다. 최근 20-off GaAs 기판을 이용한 양자점의 성장은 다른 공정과는 달리 성장조건만으로 선택적인 성장을 얻을 수 있으며 양자점의 크기가 terrace width를 벗어나지 않으므로 uniformity를 향상시킬 수 있다. 20-off GaAs 기판의 trrrace 넓이는 약 99 이지만 성장조건하에 Ga의 diffusion에 의한 step bunching 효과에 의하여 그 넓이는 변화하며 특히, 성장 두께에 따라 넓이는 증가한다. 이러한 현상을 바탕으로 20-off 기판위에 GaAs buffer 층을 1000 , 22 을 갖게 되었다. 이로써 20-off 기판을 이용할 경우,GaAs buffer 층의 두께만으로 양자점의 크기를 조절할 수 있다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.4
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• pp.174-186
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• 2004

Striations are growth-induced inhomogeneities which hamper the applications of solid-solution crystals and of doped crystals in numerous technologies. Thus the optimized performance of solid solutions often can not be exploited. The inhomogeneity problem can be solved in specific cases by achieving a distribution coefficient one in growth from melts and from solutions. Macrostep-induced striations can be suppressed by controlling the growth mode, by achieving growth on facets thereby preventing step bunching. Thermal striations are commonly assumed to be caused by convective instabilities so that reduced convection by microgravity or by damping magnetic fields was and is widely attempted to reduce such inhomogeneities. Here it will be shown that temperature fluctuations at the growth interface cause striations, and that hydrodynamic fluctuations in a quasi-isothermal growth system do not cause striations. The theoretically derived conditions were experimentally established and allowed the growth of striation-free crystals of $KTa_{1-x}Nb_xO_3$"KTN" solid solutions. Hydrodynamic variations from the accelerated crucible rotation technique ACRT did not cause striations as long as the temperature was controlled within $0.03^{\circ}$ at $1200^{\circ}C$ growth temperature. Alternative approaches to solve or reduce the segregation and striation problems in growth from melts and from solutions are discussed as well.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• International journal of advanced smart convergence
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• v.4 no.1
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• pp.137-144
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• 2015

Development of the yarn sorting equipment (khonhook) by slide way due to the principle of engineering that cause of workers on the long of motion time. The data was collected from the weaving group Ban Nongkok village, Nakornratchasima Province, THAILAND. According to the study, the step of yarn sorting (konhook) was one of the steps that affect long of motion time. The problem was the inadequate capacity equipment. The objective of research was to study and develop the yarn sorting equipment (konhook). The fabric used in the study was 64 meters in length and 1 meter in width. Researchers studied the processes the yarn sorting (konhook) which it consists of seven sub steps, 1) the thread tube setting, 2) yarn bunching, 3) tying a knot at the end of yarn, 4) looping the yarn into a pillar, 5) sorting the yarn (konhook), 6) crossing pillars and 7) taking out the yarn. Researchers focused on studying yarn sorting process (konhook) by designing and creating a device for yarn sorting (konhook) for reducing yarn sorting (konhook) time by the original method performance indicators. The results found that the developed yarn sorting equipment (konhook) ) by slide way could reduce working time from 7.24 minutes to 6.08 minutes of the original equipment yarn sorting (konhook). This means it could make the process 16.02 % faster. This also helps reducing the distance of workers' movement from 2,234 meters to 8 meters. This is 99.64 % shorter.