• ETRI Journal
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• v.38 no.1
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• pp.185-194
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• 2016

In this paper, a novel rate control scheme for low delay video coding of High Efficiency Video Coding (HEVC) is proposed. The proposed scheme is developed by considering a new temporal prediction structure of HEVC. In the proposed scheme, the relationship between bit rate and quantization step is exploited firstly to formulate an accurate quadratic rate-quantization (R-Q) model. Secondly, a method of determining the quantization parameters (QPs) for the first frames within a group of pictures is proposed. Thirdly, an accurate frame-level bit allocation method is proposed for HEVC. Finally, based on the proposed R-Q model and the target bit allocated for the frame, the QPs are predicted for coding tree units by using rate-distortion (R-D) optimization. We compare our scheme against that of three other state-of-the-art rate control schemes. Experimental results show that the proposed rate control scheme can increase the Bjøntegaard delta peak signal-to-noise ratio by 0.65 dB and 0.09 dB on average compared with the JCTVC-I0094 and JCTVC-M0036 schemes, respectively, both of which have been implemented in an HEVC test model encoder; furthermore, the proposed scheme achieves a similar R-D performance to Wang's scheme, as well as obtaining the smallest bit rate mismatch error of all the schemes.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.299-303
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• 1995

This paper charcterizes dynamics of cold tandem minns, and constructs it state-space model of which are linear time invariant, using subspace method. Step responses particularly show the influence on mass transfer delay. Input-output data set are obtained form nonlinear differential equations including mass transfer delay and nonlinearity. It is shown that the identified state-apace model well approximates the original systems dynamics.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.76.5-76
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• 2001

This paper considers the parameter estimation for the state-space model based time-delay systems in the case that the Lyapunov stability of the system is guaranteed. In order to estimate the parameters, two estimation methods can be proposed which are known as the parallel model and the series parallel model. It is shown that the parameters can be estimated using each method, and also certied that the results are correct by simulations.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.90.2-90
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• 2002

A new integral controller is proposed for time-delay plants. The proposed controller has Davison type structure and utilizes a simplified state predictor instead of the optimal state predictor for the extended system. The simplified predictor is introduced by a trick similar to that used in the Smith predictor. As a systematic method for designing the proposed controller, the application of the loop transfer recovery (LTR) technique is considered. For the plant input side and the output side, explicit representations of the sensitivity matrices achieved by enforcing the formal LTR procedure using Riccati equations are obtained. A numerical example is presented to compare the asymptotic...

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.137-143
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• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.4
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• pp.188-200
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• 2001

This paper presents a technique for reconstructing converter line currents using the information from a single current sensor in the DC-link for voltage-source PWM converters. When three-Phase input currents cannot be reconstructed, three methods to acquire the input current are compared. Two of them are methods of modifying the switching state (I, II), another is a method of using the predictive state observer. Also, compensation of sampling delay, and a simultaneous sample value of input currents in the center of a switching period are included. Suitable criteria for the comparison are identified, and the differences in the performance of these methods are investigated through experimental results for a typical V-S PWM converter rated at 10kVA.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.163-169
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• 1998

In this paper, we consider the problem of designing H$\infty$ state feedback controller for the generalized time systems with delayed states and control inputs in continuous and discrete time cases, respectively. The generalized time delay system problems are solved on the basis of LMI(linear matrix inequality) technique considering time delays. The sufficient condition for the existence of controller and H$\infty$ state feedback controller design methods are presented. Also, using some changes of variables and Schur complements, the obtained sufficient condition can be rewritten as a LMI form in terms of transformed variables. The propose controller design method can be extended into the problem of robust H$\infty$ state feedback controller design method easily.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.1
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• pp.171-178
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• 2017

This paper studies the state estimation problem for static neural networks with time-varying delay. Unlike other studies, the controller scheme, which involves time-varying sampling and uncertainties, is first employed to design the state estimator for delayed static neural networks. Based on Lyapunov functional approach and linear matrix inequality technique, the non-fragile sampled-data estimator is designed such that the resulting estimation error system is globally asymptotically stable with $H_{\infty}$ performance. Finally, the effectiveness of the developed results is demonstrated by a numerical example.

• International Journal of Control, Automation, and Systems
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• v.5 no.1
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• pp.70-78
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• 2007

We prove that TCP Vegas globally converges to its equilibrium point in finite time assuming no feedback information delay. We analyze a continuous-time TCP Vegas model with discontinuity and high nonlinearity. Using the upper right-hand derivative and applying the comparison lemma, we cope with the discontinuous signum function in the TCP Vegas model; using a change of state variables, we deal with the high nonlinearity. Although we ignore feedback information delay in analyzing the model of TCP Vegas, the simulation results illustrate that TCP Vegas in the presence of feedback information delay shows very similar dynamic trends to TCP Vegas without feedback information delay. Consequently, dynamic properties of TCP Vegas without feedback information delay can be used to estimate those of TCP Vegas in the presence of feedback information delay.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.