• Journal of Pharmacopuncture
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• v.25 no.2
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• pp.71-78
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• 2022

Objectives: Post-term pregnancy is a condition associated with increased maternal and fetal complications. Administration of castor oil causes cervical stimulation by increasing the production of prostaglandins. We examined the effects of castor oil on cervical ripening and labor induction through a systematic review and meta-analysis. Methods: The search process was performed to obtain relevant articles from databases including Pubmed, Cochrane library, Scopus, Science direct, SID, Iran Medex, and Google Scholar using the English keywords of cervical ripening, post-term, castor oil, labor induction, Bishop score, and pregnancy considering all possible combinations without time constraints and their Persian equivalents from national databases. Results: A total of eight related articles from the 19 primary studies were extracted and systematically reviewed. According to a cumulative chart, the difference in the post-intervention Bishop score was statistically significant (standard mean difference [SMD]: 1.64, 95% confidence interval [CI]: 1.67-2.11, p = 0.001), indicating an effect of castor oil on increasing the Bishop score. In addition, the difference in labor induction was statistically significant after the intervention (odds ratio: 11.67, 95% CI: 3.34-40.81, p = 0.001), indicating an effect of castor oil on increasing the odds ratio of labor induction (experience of vaginal delivery). Conclusion: This meta-analysis showed that oral administration of castor oil is effective for cervical ripening and labor induction. Midwives should closely monitor pregnant women with prolonged labor and collaborate with obstetricians to employ castor oil as a safe intervention to induce cervical ripening and labor to prevent undue caesarean surgery.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Safety and Health at Work
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• v.9 no.1
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• pp.1-9
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• 2018

Background: Work-related musculoskeletal disorders are the most important problems among professions particularly, dentists. This study was conducted to determine the prevalence of musculoskeletal disorders in various parts of the body in Iranian dentists by using systematic review and meta-analysis. Methods: This systematic review and meta-analysis was based on preferred reporting items for systematic reviews and meta-analyses (PRISMA) guidelines and searching in national databases such as SID, Magiran, Irandoc, IranMedex, and Medlib, and international databases such as MedLine, Web of Sciences, Scopus, PubMed, ScienceDirect, Cochrane, Embase, Springer, Wiley Online Library, Ebsco, CEBM, and Google Scholar search engine which were published by January 1, 2017. Researched keywords were in Persian and their standard English equivalents were in accordance with their MeSH. The obtained documents were analyzed using Comprehensive Meta-analysis version 2. Results: According to 23 studies through 2,531 Iranian dentists which took part in this study, prevalence of skeletal disorders in Iranian dentists has been 17.6% [confidence interval (CI) 95%:11.7-25.5] in knees, 33.2% (CI 95%:24.1-43.8) in shoulders, 33.4% (CI 95%: 26.8-40.8) in the thorax, 51.9% (CI 95%:46.7-57.2) in necks, 33.7% (CI 95%:28.2-39.6) in wrists/hands, 12.9% (CI 95%:7.7-20.6) in elbows, 37.3% (CI 95%: 31.5-43.5) in lower back, 11.9% (CI 95%:8.7-16.1) in thighs, 12.9% (CI 95%:3.8-36) in the foot, and 10.5% (CI 95%:7-15.4) in legs. Conclusion: Considering the high prevalence of musculoskeletal disorders in Iranian dentists, ergonomics should be included as a lesson in preclinic and also, reeducation courses for ergonomics basics should be executed for graduate dentists.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.79-84
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• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.

• Journal of Korean Society of Archives and Records Management
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• v.10 no.2
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• pp.75-99
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• 2010

Digital resources are widely used in our modern society. However, we are facing fundamental problems to maintain and preserve digital resources over time. Several standard methods for preserving digital resources have been developed and are in use. It is widely recognized that metadata is one of the most important components for digital archiving and preservation. There are many metadata standards for archiving and preservation of digital resources, where each standard has its own feature in accordance with its primary application. This means that each schema has to be appropriately selected and tailored in accordance with a particular application. And, in some cases, those schemas are combined in a larger frame work and container metadata such as the DCMI application framework and METS. There are many metadata standards for archives of digital resources. We used the following metadata standards in this study for the feature analysis me metadata standards - AGLS Metadata which is defined to improve search of both digital resources and non-digital resources, ISAD(G) which is a commonly used standard for archives, EAD which is well used for digital archives, OAIS which defines a metadata framework for preserving digital objects, and PREMIS which is designed primarily for preservation of digital resources. In addition, we extracted attributes from the decision tree defined for digital preservation process by Digital Preservation Coalition (DPC) and compared the set of attributes with these metadata standards. This paper shows the features of these metadata standards obtained through the feature analysis based on the records lifecycle model. The features are shown in a single frame work which makes it easy to relate the tasks in the lifecycle to metadata elements of these standards. As a result of the detailed analysis of the metadata elements, we clarified the features of the standards from the viewpoint of relationships between the elements and the lifecycle stages. Mapping between metadata schemas is often required in the long-term preservation process because different schemes are used in the records lifecycle. Therefore, it is crucial to build a unified framework to enhance interoperability of these schemes. This study presents a basis for the interoperability of different metadata schemas used in digital archiving and preservation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.876-884
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• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.