• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 제4회 영호남학술대회 논문집
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• pp.109-122
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• 2002

The standard capacitor must have not only precise value of the capacitance but also the basic properties of low dielectric loss tangent. In the reforming process of capacitors, the dielectric loss tangent must be also reformed. In this paper, the development of standard capacitors of 10 and 100pF for the dielectric loss tangent standard using $Al_{2}O_{3}$ Crystal and the measurement of dielectric loss tangent are discussed. The dielectric loss tangent depends upon the surface between electrode and dielectric in capacitor. With using the Electric Field Simulator, precise design values of electrode are simulated. For the purpose of measuring capacitance effect just in the dielectric, 3-Terminal and 4-Terminal Pair configuration are applied respectively at the electrode and the connector for the measuring equipment. As stated above method, the standard capacitors of 10 and l00pF for the establishment of the dielectric loss tangent standard using the $Al_{2}O_{3}$ Crystal are made with low dielectric loss tangent less than 10-4.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제55권8호
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• pp.403-407
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• 2006

Standard capacitors, as like as Hamon resistor standards, of series connection/parallel connection ratio $10{\mu}F/1000{\mu}F\;and\;100{\mu}F/10000{\mu}F$ were fabricated for calibration of impedance bridges or analyzers with measuring ranges up to 1 F. The calculated correction terms to the ratio of one measured value in series connection to the value in parallel connection were evaluated to be $1.92{\times}10^{-7}$. These capacitors were designed to be used not only as 100:1 capacitance standards but also as single capacitors or decade capacitors with decade values at frequencies up to 1 kHz.

• 대한전기학회논문지:전력기술부문A
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• 제48권7호
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• pp.839-846
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• 1999

This paper presents an efficient algorithm for determining the location, size and number of capacitors in unbalanced radial distribution system. The objective function formulated consists of two terms: cost for energy loss and cost related to capacitor purchase and capacitor installation. The cost function associated with capacitor placement is considered as step function due to banks of standard discrete capacities. Genetic algorithms(GA) are used to obtain the population is derived. The strings in each population consist of the bus number index and size of capacitors to be installed. In order to determine the number of capacitor placement, the length mutation operator is used. Its efficiency is proved through the application in unbalanced radial distribution systems made of 10 buses with 9 distribution lines and 25 buses with 24 distribution lines.

• 대한전기학회논문지:전력기술부문A
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• 제52권6호
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• pp.316-324
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• 2003

This paper applied Elite-based Simplex-GA hybrid approach combined with Muptipop-GA (ESGA) to determining the location, size and number of capacitors to improve voltage profile and minimize power losses in unbalanced distribution systems. One of the main obstacles in applying GA to complex problems has been the high computational cost due to their slow convergence rate. To alleviate this difficulty, ESGA approach was developed that combines Elite-based Simplex-GA hybrid approach with Muptipop-GA. The objective function formulated consists of two terms: cost for energy losses and cost related to capacitor purchase and capacitor installation. The cost function associated with capacitor placement is considered as a step function due to banks of standard discrete capacities. Its efficiency was proved through the application in IEEE 13 bus and 34 bus test systems and was compared with several methods using GA.

• 전기학회논문지
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• 제60권2호
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• 전기학회논문지
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• 제57권9호
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• pp.1546-1551
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• 2008

This paper is concerned with the problems of accurate losses segregation in capacitor-run single phase motor. Segregation of losses in single phase induction motor is more complicated than that in three phase induction motor, because of the backward magnetic field component in the motor. Generally there are two methods for losses segregation of single phase induction motor. The one is relatively complicated method based on parameter estimation of single phase induction motor. By the way, the other one is simplified method based on IEEE Standard 114. All of the methods for the experimental determination of single phase induction motor losses are studied in this paper. Since the IEEE Standard is not possible to be applied for all type of single phase induction motors, we modified that method to apply for losses segregation of capacitor-run single phase induction motor as unifying the method based on parameter estimation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.15-21
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• 2013

In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

• 전기학회논문지P
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• 제52권4호
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.