• Journal of Korean Society for Quality Management
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• v.42 no.3
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.11
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• pp.226-232
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• 2020

The Stage-Gate is a market-oriented model that aims to launch new products on the market. Therefore, it can be appropriately introduced and applied to the operation and management of NSSCP, which is undergoing demonstration projects for Daegu and Siheung. In addition, smart cities have the characteristics of convergence and complex among various innovative technologies. When the Stage-Gate is introduced, the performance can be managed centering on the outcomes for each research institution. Therefore, the NSSCP is applying the Stage-Gate for the first time among national R&D projects to improve the quality of the research results and to demonstrate and commercialize them successfully. This paper reviews the operation results of the 1st and 2nd years when the State-Gate was introduced and analyzes the opinions of an R&D management agency, research institutes, and gate reviewers to present the supplementary and improvements for applying to the evaluation process for the next year. When operating the Stage-Gate by optimizing the situation for each project and being wary of inefficiencies caused by the rigid operation, it is expected that flexible evaluation for each outcome will be possible according to the convergence characteristics of smart cities.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.43 no.2
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• pp.65-71
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• 2020

Worldwide plant market keeps maintaining steady growth rate and along with this trend, domestic plant market and its contractors also maintain such growing tendency. However, in spite of its external growth, win-win growth of domestic material industry that occupies the biggest share in plant industry cost portion is extremely marginal in reality. Domestic plant material suppliers are required to increase awareness of domestic material brand by securing quality and reliability of international standard through improvement of design quality superior to that of overseas material suppliers. Improvement of design quality of plant material becomes an essential element, not an option, for survival of domestic plant industry and its suppliers. Under this background, in this study, priority and importance by each evaluation index was analyzed by materializing plant design stage through survey of experts and defining evaluation index by each design stage and based on this analysis result, evaluation index of stage-gate based decision-making process that may improve design quality of plant material was suggested. It is considered that by utilizing evaluation index of stage-gate based decision-making process being suggested in this study, effective and efficient decision-making of project decision-makers would be enabled and it would be contributory to improve design quality of plant material.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.9 no.6
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• pp.21-28
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• 2010

This study shows an optimization procedure for an automatic determination on the gate position to ensure the fill-uniformity within a part cavity by using the injection molding simulation. For an optimization, the maximum pressure-difference within a part cavity induced at the stage of filling is used to evaluate degree of fill-uniformity. In addition, a direct search scheme based on the reduction of design space is developed and applied in the optimization problem. This corresponding proposed methodology was applied in the optimization on the gate location for a CD-tray molding, as a result, showed the improvement of the fill-uniformity within the cavity.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.2 no.2
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• pp.33-37
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• 2001

The synthesis of gates of injection-molded parts has been done empirically, since it requires profound knowledge about the gate design,. which is not available to designers through current CAD systems. GATEWAY is a knowledge module which contains knowledge to Permit non-experts as well as mold design experts to generate acceptable gate design of injection-molded parts. A knowledge-based CAD system is constructed by adding the knowledge module, GATEWAY, for gate synthesis and appropriate CAE programs for mold design analysis to an existing geometric modeler to provide designers, at the initial stage, with comprehensive process knowledge for gate synthesis. Performance analysis and feature-based geometric modeling.

• Korea-Australia Rheology Journal
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• v.12 no.1
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• pp.83-92
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• 2000

In resin transfer molding (RTM) process, preplaced fiber mat is set up in a mold and thermoset resin is injected into the mold. An important interest in RTM process is to minimize cycle time without sacrificing part quality or increasing cost. In this study, the numerical simulation and optimization process in filling stage were conducted in order to determine the optimum gate locations. Control volume finite element method (CVFEM) was used in this numerical analysis with the coordinate transformation method to analyze the complex 3-dimensional structure. Experiments were performed to monitor the flow front to validate simulation results. The results of numerical simulation predicted well the experimental results with every single, simultaneous and sequential injection procedure. We performed the optimization analysis for the sequential injection procedure to minimize fill time. The complex geometry of an automobile bumper core was chosen. Genetic algorithm was used in order to determine the optimum gate locations with regard to 3-step sequential injection case. These results could provide the information of the optimum gate locations in each injection step and could predict fill time and flow front.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.