• 품질경영학회지
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• 제42권3호
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• 한국산학기술학회논문지
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• 제21권11호
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• pp.226-232
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• 2020

Stage-Gate 프로세스는 신제품을 아이디어에서 출시로 옮기기 위한 개념 및 운영 모델로, 다양한 신제품 개발 및 연구개발사업에 적용되고 있다. Stage-Gate는 신제품을 시장에 출시하는 것을 목표로 하는 시장 지향적 모델이므로, 대구광역시와 시흥시를 대상으로 실증사업을 진행 중인 스마트시티 혁신성장동력 프로젝트의 운영·관리에 적절히 도입 및 응용 가능하다. 또한 스마트시티는 다양한 혁신 기술 간 융·복합적 특성을 갖는데, Stage-Gate 도입 시, 이를 세분화하여 연구 기관별 성과물 중심의 성과 관리가 가능해진다. 따라서 스마트시티 혁신성장동력 프로젝트(NSSCP: National Strategic Smart City Program)는 국가연구개발사업 최초로 투자 효율성 제고와 연구 성과의 품질 향상, 성공적인 실증 및 사업화를 위하여 Stage-Gate를 적용하였다. 본 논문은 State-Gate 도입 1~2차년도 운영 결과를 검토하고 전문 기관, 연구 기관, 관문심사위원의 의견을 분석하여 향후 차년도 평가체계 운영과 타 연구과제에 적용을 위한 보완 및 개선사항을 제시하였다. Stage-Gate 방법론에 과도하게 몰입되어 경직된 운영에 따른 비효율을 경계하고 해당 사업의 실정에 최적화하여 운영한다면, 스마트시티의 융복합·다학제적 특성에 맞게 성과물 유형에 따른 유연한 평가가 가능할 것으로 기대된다.

• 산업경영시스템학회지
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• 제43권2호
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• pp.65-71
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• 2020

Worldwide plant market keeps maintaining steady growth rate and along with this trend, domestic plant market and its contractors also maintain such growing tendency. However, in spite of its external growth, win-win growth of domestic material industry that occupies the biggest share in plant industry cost portion is extremely marginal in reality. Domestic plant material suppliers are required to increase awareness of domestic material brand by securing quality and reliability of international standard through improvement of design quality superior to that of overseas material suppliers. Improvement of design quality of plant material becomes an essential element, not an option, for survival of domestic plant industry and its suppliers. Under this background, in this study, priority and importance by each evaluation index was analyzed by materializing plant design stage through survey of experts and defining evaluation index by each design stage and based on this analysis result, evaluation index of stage-gate based decision-making process that may improve design quality of plant material was suggested. It is considered that by utilizing evaluation index of stage-gate based decision-making process being suggested in this study, effective and efficient decision-making of project decision-makers would be enabled and it would be contributory to improve design quality of plant material.

• 한국통신학회논문지
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• 제14권3호
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• pp.189-196
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• 1989

본 논문에서는 BICMOS 게이트 어레이 시스템 구성시 내부의 논리회로 부분은 CMOS 소자로 입출력부는 바이폴라 소자를 이용할 수 있는 공정과 소자 개발을 하고자 하였다. BICMOS게이트 어레이 공정은 폴리게이트 p-well CMOS 공정을 기본으로 하였고, 소자설계의 기본개념은 공정흐름을 복잡하지 않게 하면서 바이폴라, CMOS 소자 각각의 특성을 좋게 하는데 두었다. 시험결과로서, npn1 트랜지스터의 hFE 특성은 120(Ic=1mA) 정도이고, CMOS 소자에서는 n-채널과 p-채널이 각각 1.25um, 1.35um 까지는 short channel effect 현상이 나타나지 않았고, 41stage ring oscillator의 게이트당 delay 시간은 0.8ns이었다.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• 한국기계가공학회지
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• 제9권6호
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• pp.21-28
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• 2010

This study shows an optimization procedure for an automatic determination on the gate position to ensure the fill-uniformity within a part cavity by using the injection molding simulation. For an optimization, the maximum pressure-difference within a part cavity induced at the stage of filling is used to evaluate degree of fill-uniformity. In addition, a direct search scheme based on the reduction of design space is developed and applied in the optimization problem. This corresponding proposed methodology was applied in the optimization on the gate location for a CD-tray molding, as a result, showed the improvement of the fill-uniformity within the cavity.

• 한국산학기술학회논문지
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• 제2권2호
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• pp.33-37
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• 2001

본 논문은 사출성형제품의 게이트 설계를 합리적으로 수행하기 위해 사출금형설계전문가의 축적된 지식과 경험을 발췌·정리하여 지식베이스를 작성하였으며, 설계에 필요한 제품의 형상정보를 제공하기 위해 총칭형상과 특징형상 개념을 이용하여 특징형상을 정의하였다. 또한 지식베이스를 통해 산출된 설계결과를 기하학적 모델러와의 인터페이스를 통해 3차원 형상으로 보여지도록 하였으며 최종 생성된 3차원 기하학적 형상정보는 CAE 모듈이나 CAPP 모듈에서의 후속작업을 위해 제공될 수 있도록 구축되었다.

• Korea-Australia Rheology Journal
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• 제12권1호
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• pp.83-92
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• 2000

In resin transfer molding (RTM) process, preplaced fiber mat is set up in a mold and thermoset resin is injected into the mold. An important interest in RTM process is to minimize cycle time without sacrificing part quality or increasing cost. In this study, the numerical simulation and optimization process in filling stage were conducted in order to determine the optimum gate locations. Control volume finite element method (CVFEM) was used in this numerical analysis with the coordinate transformation method to analyze the complex 3-dimensional structure. Experiments were performed to monitor the flow front to validate simulation results. The results of numerical simulation predicted well the experimental results with every single, simultaneous and sequential injection procedure. We performed the optimization analysis for the sequential injection procedure to minimize fill time. The complex geometry of an automobile bumper core was chosen. Genetic algorithm was used in order to determine the optimum gate locations with regard to 3-step sequential injection case. These results could provide the information of the optimum gate locations in each injection step and could predict fill time and flow front.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.