• 한국공작기계학회논문집
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• 제12권6호
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• pp.8-13
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• 2003

CFRP composite has a lot of merits such as mechanical characteristic, light weight and thermal resistance. For these merits CFRP is applied to so many industrial area. In order for the composite materials to be used in the aircraft structures or machine elements, accurate surfaces for bearing mounting or joints must be provided, which require precise machining. In this paper, the relationship between the stack thickness and drill diameter is examined from the drilling experiment, which is the drilling of 16, 32, 48p1ies specimen with the ${\phi}8$, ${\phi}10$, ${\phi}12mm$ cemented carbide drill. The results are analyzed with consideration of cutting force, stack thickness and drill diameter.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2003년도 춘계학술대회 논문집
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• pp.190-195
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• 2003

CFRP composite has a lot of merits such as mechanical characteristic, light weight, and thermal resistance. For these merits CFRP is applied to so many industrial area. In this paper, the relationship between the stack thickness and drill diameter is examined from the drilling experiment, which is the drilling of 16, 32, 48 plies specimen with the $\phi$8, $\phi$10, $\phi$12mm cemented carbide drill. The results are analyzed with consideration of cutting force, stack thickness and drill diameter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• 한국재료학회지
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• 제22권8호
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• pp.403-408
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• 2012

A sample of ultra low carbon IF steel was processed by six-layer stack accumulative roll-bonding (ARB) and annealed. The ARB was conducted at ambient temperature after deforming the as-received material to a thickness of 0.5 mm by 50% cold rolling. The ARB was performed for a six-layer stacked, i.e. a 3 mm thick sheet, up to 3 cycles (an equivalent strain of ~7.0). In each ARB cycle, the stacked sheets were, first, deformed to 1.5 mm thickness by 50% rolling and then reduced to 0.5 mm thickness, as the starting thickness, by multi-pass rolling without lubrication. The specimen after 3 cycles was then annealed for 0.5 h at various temperatures ranging from 673 to 973 K. The microstructural evolution with the annealing temperature for the 3-cycle ARB processed IF steel was investigated in detail by transmission electron microscopy observation. The ARB processed IF steel exhibited mainly a dislocation cell lamella structure with relatively high dislocation density in which the subgrains were partially observed. The selected area diffraction (SAD) patterns suggested that the misorientation between neighboring cells or subgrains was very small. The thickness of the grains increased in a gradual way up to 873 K, but above 898 K it increased drastically. As a result, the grains came to have an equiaxed morphology at 898 K, in which the width and the thickness of the grains were almost identical. The grain growth occurred actively at temperatures above 923 K.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1043-1044
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• 2011

This paper discusses the electromagnetic and mechanical design considerations to improve the design accuracy and power to mass ratio of multi-stack axial flux permanent magnet synchronous generator (AFPMSG). Design accuracy of multi-stack AFPMSG for direct drive wind turbine application is improved by considering magnetic flux leakages and fringing effect. FEM structural analysis is utilized to increase power to mass ratio of three-stack AFPMSG by reducing the rotor yoke thickness considering magnetic and centrifugal forces and Von Mises stress distribution.

• Journal of Advanced Marine Engineering and Technology
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• 제39권4호
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• pp.374-380
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• 2015

본 연구에서는 연료전지 캐소드 가스 확산층에서의 물의 영향이 연료전지 성능에 미치는 영향을 검토하기 위하여 연료전지 스택의 부하 변동에 따른 가스 확산층에서의 2상 현상의 구현이 가능한 동적 모델을 개발하였다. 개발된 모델에 대하여 2상의 영향에 의한 연료전지 부하변동에 따른 연료전지 스택 성능, 가스 확산층 내부에서의 물 증기와 산소의 농도분포, 가스 확산층의 두께 및 다공성이 연료전지 스택 전압에 미치는 영향에 대하여 검토하였다. 그 결과 본 연구의 범위 내에서 연료전지 스택 전압은 부하에 관계없이 2상 모델이 1상 모델보다 낮아짐을 알 수 있다. 촉매층 부근 가스 확산층에서의 산소 농도는 가장 낮고 물 증기의 농도는 가장 높음을 알 수 있었다. 또한, GDL의 두께가 두꺼울수록 GDL의 다공성이 작을수록 연료전지 스택 전압이 낮아짐을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• 한국재료학회지
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• 제23권3호
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• pp.206-210
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• 2013

In the segmented-in-series solid-oxide fuel cells (SIS-SOFCs), fabrication techniques which use decalcomania paper have many advantages, i.e., an increased active area of the electrode; better interfacial adhesion property between the anode, electrolyte and cathode; and improved layer thickness uniformity. In this work, a cell-stack was fabricated on porous ceramic flattened tube supports using decalcomania paper, which consists of an anode, electrolyte, and a cathode. The anode layer was $40{\mu}m$ thick, and was porous. The electrolyte layers exhibited a uniform thickness of about $20{\mu}m$ with a dense structure. Interfacial adhesion was improved due to the dense structure. The cathode layers was $30{\mu}m$ thick with porous structure, good adhesion to the electrolyte. The ohmic resistance levels at 800, 750 and $700^{\circ}C$ were measured, showing values of 1.49, 1.58 and $1.65{\Omega}{\cdot}cm^2$, respectively. The polarization resistances at 800, 750 and $700^{\circ}C$ were measured to be 1.63, 2.61 and $4.17cm^2$, respectively. These lower resistance values originated from the excellent interfacial adhesion between the anode, electrolyte and cathode. In a two-cell-stack SOFC, open-circuit voltages(OCVs) of 1.915, 1.942 and 1.957 V and maximum power densities(MPD) of 289.9, 276.1 and $220.4mW/cm^2$ were measured at 800, 750 and $700^{\circ}C$, respectively. The proposed fabrication technique using decalcomania paper was shown to be feasible for the easy fabrication of segmented-in-series flattened tube SOFCs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.74-74
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• 2009

The ArF PR mask was. developed to overcome the limit. of sub 40nm patterning technology with KrF PR. But ArF PR difficult to meet the required PR selectivity by thin PR thickness. So need to the multi-stack mask such as amorphous carbon layer (ACL). Generally capacitively coupled plasma (CCP) etcher difficult to make the high density plasma and inductively coupled plasma (ICP) type etcher is more suitable for multi stack mask etching. Hybrid Coupled Plasma source (HCPs) etcher using the 13.56MHz RF power for ICP source and 2MHz and 27.12MHz for bias power was adopted to improve the process capability and controllability of ion density and energy independently. In the study, the oxide trench which has the multi stack layer process was investigated with the HCPs etcher (iGeminus-600 model DMS Corporation). The results were analyzed by scanning electron microscope (SEM) and it was found that etching characteristic of oxide trench profile depend on the multi-stack mask.