• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.4
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• pp.517-522
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• 2013

The spurious electromagnetic radiation is generated due to the RF unbalanced current on a conductive cable connecting an electronic device to another. A metamaterial-based filtering geometry with frequency selectivity is suggested to reduce the radiation with a bandgap structure, where the right-handed inductance and capacitance stem from the transmission-like configuration between the cable and the metal protrusion, and the left-handed components come from the narrow cavities. The effect of the structure on the unbalanced current pulse and its spurious radiation is presented in the FDTD-method frame work.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.623-638
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• 2012

The volume of fluid (VOF) model of FLUENT and the lattice Boltzmann method (LBM) are used to simulate two-phase flows. Both methods are validated for static and dynamic bubble test cases and then compared to experimental results. The VOF method does not reduce the spurious currents of the static droplet test and does not satisfy the Laplace law for small droplets at the acceptable level, as compared with the LBM. For single bubble flows, simulations are executed for various Eotvos numbers, Morton numbers and Reynolds numbers, and the results of both methods agree well with the experiments in the case of low Eotvos numbers. For high Eotvos numbers, the VOF results deviated from the experiments. For multiple bubbles, the bubble flow characteristics are related by the wake of the leading bubble. The coaxial and oblique coalescence of the bubbles are simulated successfully and the subsequent results are presented. In conclusion, the LBM performs better than the VOF method.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• The Korean Journal of Applied Statistics
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• v.29 no.6
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• pp.999-1005
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• 2016

The advent of big data brings the opportunity to answer many open scientic questions but also presents some interesting challenges. Main features of contemporary datasets are the high dimensionality and massive sample size. In this paper, we give an overview of major challenges caused by these two features: (1) noise accumulation and spurious correlations in high dimensional data; (ii) computational scalability for massive data. We also provide applications of big data in various fields including forecast of disasters, digital humanities and sabermetrics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.619-620
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• 2006

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of $0.76mm^2$.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.182.2-182.2
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• 2012

If the satellite has the magnetic material or magnetic moment, the satellite is affected by the earth magnetic field by the space environment in Geostational orbit. The aim of this paper is to assess the satellite magnetic momentum which is an input to ADCS(Altitude Determination Control Subsystem) analyses to assess spurious torques. The magnetic momentum at satellite level is due to magnetic momentum generated by each unit which is due to internal currents circulation or to the presence of magnetic components. Also the magnetic momentum at satellite level is due to circulation of the DC supply current from PSR(Power Supply Regulator) to each unit. As introducing the intrinsic contribution of each unit and the magnetic moment based on the current return through the structure, this paper assess the satellite magnetic moment.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.9
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• pp.798-805
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• 2015

This paper proposes Relaxation Oscillator with Random Number Generator to minimize electromagnetic interference (EMI) noise. DC-DC Converter with Relaxation Oscillator is presented how much spurious noise effects to RF Receiver system. The main frequency of the proposed Relaxation oscillator is 7.9 MHz to operate it and add temperature compensation block to be applied to the frequency compensation in response to temperature changes. The DC-DC Converter Spurious noise is reduced up to 20 dB through changing frequency randomly. It is fabricated in $0.18{\mu}m$ CMOS technology. The active area occupies an area of $220{\mu}m{\times}280{\mu}m$. The supply voltage is 1.8 V and current consumption is $500{\mu}A$.