• 제목/요약/키워드: Spurious Current

검색결과 22건 처리시간 0.03초

주파수 선택도를 가지는 메타재질구조를 이용한, 선로상의 전류펄스에 의한 불요방사 억제기법 (A Method to Suppress the Spurious Radiation due to the Current Pulse on the Cable using the Frequency Selective Metamaterial Structure)

  • 강승택;양인규;김형석
    • 전기학회논문지
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    • 제62권4호
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    • pp.517-522
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    • 2013
  • The spurious electromagnetic radiation is generated due to the RF unbalanced current on a conductive cable connecting an electronic device to another. A metamaterial-based filtering geometry with frequency selectivity is suggested to reduce the radiation with a bandgap structure, where the right-handed inductance and capacitance stem from the transmission-like configuration between the cable and the metal protrusion, and the left-handed components come from the narrow cavities. The effect of the structure on the unbalanced current pulse and its spurious radiation is presented in the FDTD-method frame work.

A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

  • Heo, Yun-Seong;Oh, Hyun-Seok;Jeong, Hae-Chang;Yeom, Kyung-Whan
    • Journal of electromagnetic engineering and science
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    • 제11권2호
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    • pp.105-112
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    • 2011
  • In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

A COMPARATIVE STUDY OF LATTICE BOLTZMANN AND VOLUME OF FLUID METHOD FOR TWO-DIMENSIONAL MULTIPHASE FLOWS

  • Ryu, Seung-Yeob;Ko, Sung-Ho
    • Nuclear Engineering and Technology
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    • 제44권6호
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    • pp.623-638
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    • 2012
  • The volume of fluid (VOF) model of FLUENT and the lattice Boltzmann method (LBM) are used to simulate two-phase flows. Both methods are validated for static and dynamic bubble test cases and then compared to experimental results. The VOF method does not reduce the spurious currents of the static droplet test and does not satisfy the Laplace law for small droplets at the acceptable level, as compared with the LBM. For single bubble flows, simulations are executed for various Eotvos numbers, Morton numbers and Reynolds numbers, and the results of both methods agree well with the experiments in the case of low Eotvos numbers. For high Eotvos numbers, the VOF results deviated from the experiments. For multiple bubbles, the bubble flow characteristics are related by the wake of the leading bubble. The coaxial and oblique coalescence of the bubbles are simulated successfully and the subsequent results are presented. In conclusion, the LBM performs better than the VOF method.

10-Bit 200-MS/s Current-Steering DAC Using Data-Dependant Current-Cell Clock-Gating

  • Yang, Byung-Do;Seo, Bo-Seok
    • ETRI Journal
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    • 제35권1호
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    • pp.158-161
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    • 2013
  • This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

고차원 대용량 자료분석의 현재 동향 (Current trends in high dimensional massive data analysis)

  • 장원철;김광수;김정연
    • 응용통계연구
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    • 제29권6호
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    • pp.999-1005
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    • 2016
  • 빅 데이터의 출현은 여러가지 과학적 난제에 대답 할 수 있는 기회를 제공하지만 흥미로운 도전을 또한 제공한다. 이러한 빅데이터의 주요 특징으로 "고차원"과 "대용량"을 들 수가 있다. 본 논문은 이러한 두 가지 특징에 동반되는 다음과 같은 도전문제에 대한 개요를 제시한다 : (1) 고차원 자료에서의 소음 축적과 위 상관 관계; (ii) 대용량 자료분석을 위한 계산 확장성. 또한 본 논문에서는 재난예측, 디지털 인문학과 세이버메트릭스 등 다양한 분야에서 빅 데이터의 다양한 응용사례를 제공한다.

A 3 V 12b 100 MS/s CMOS D/A Converter for High-Speed Communication Systems

  • Kim, Min-Jung;Bae, Hyuen-Hee;Yoon, Jin-Sik;Lee, Seung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제3권4호
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    • pp.211-216
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    • 2003
  • This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

DS-CDMA UWB를 위한 6Bit 2.704Gs/s DAC (6Bit 2.704Gs/s DAC for DS-CDMA UWB)

  • 정재진;구자현;임신일;김석기
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.619-620
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    • 2006
  • This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of $0.76mm^2$.

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GEO Satellite Magnetic Momentum Assessment

  • 양정환;김의찬;구자춘;이상곤
    • 천문학회보
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    • 제37권2호
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    • pp.182.2-182.2
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    • 2012
  • If the satellite has the magnetic material or magnetic moment, the satellite is affected by the earth magnetic field by the space environment in Geostational orbit. The aim of this paper is to assess the satellite magnetic momentum which is an input to ADCS(Altitude Determination Control Subsystem) analyses to assess spurious torques. The magnetic momentum at satellite level is due to magnetic momentum generated by each unit which is due to internal currents circulation or to the presence of magnetic components. Also the magnetic momentum at satellite level is due to circulation of the DC supply current from PSR(Power Supply Regulator) to each unit. As introducing the intrinsic contribution of each unit and the magnetic moment based on the current return through the structure, this paper assess the satellite magnetic moment.

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배터리 전류의 정밀 측정을 위한 단일 비트 2차 CIFF 구조 델타 시그마 모듈레이터 (A Single-Bit 2nd-Order CIFF Delta-Sigma Modulator for Precision Measurement of Battery Current)

  • 배기경;천지민
    • 한국정보전자통신기술학회논문지
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    • 제13권3호
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    • pp.184-196
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    • 2020
  • 본 논문에서는 배터리 관리 시스템 (BMS)에서 2차 전지 배터리를 통해 흐르는 전류의 정밀한 측정을 위한 cascaded-of-integrator feedforward (CIFF) 구조의 단일 비트 2차 델타-시그마 모듈레이터를 제안하였다. 제안된 모듈레이터는 2개의 스위치드 커패시터 적분기, 단일 비트 비교기, 비중첩 클록 발생기 및 바이어스와 같은 주변 회로로 구현하였다. 제안된 구조는 낮은 공통 모드 입력 전압을 가지는 low-side 전류 측정 방법에 적용되도록 설계되었다. Low-side 전류 측정 방법을 사용하면 회로 설계에 부담이 줄어들게 되는 장점을 가진다. 그리고 ±30mV 입력 전압을 15비트 해상도를 가지는 ADC로 분해하기 때문에 추가적인 programmable gain amplifier (PGA)를 구현할 필요가 없어 수 mW의 전력소모를 줄일 수 있다. 제안된 단일 비트 2차 CIFF 델타-시그마 모듈레이터는 350nm CMOS 공정으로 구현하였으며 5kHz 대역폭에 대해 400의 oversampling ratio (OSR)로 95.46dB의 signal-to-noise-and-distortion ratio (SNDR), 96.01dB의 spurious-free dynamic range (SFDR) 및 15.56비트의 effective-number-of-bits (ENOB)을 달성하였다. 델타 시그마 모듈레이터의 면적 및 전력 소비는 각각 670×490㎛2 및 414㎼이다.

랜덤 수 생성 회로를 이용한 EMI Noise 저감 회로 (The EMI Noise Reduction Circuit with Random Number Generator)

  • 김성진;박주현;김상윤;구자현;김형일;이강윤
    • 한국전자파학회논문지
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    • 제26권9호
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    • pp.798-805
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    • 2015
  • 본 논문에서는 랜덤 수 생성 회로를 통해 Relaxation Oscillator의 주파수를 불규칙하게 변환하여 EMI Noise를 최소화하는 방법을 제시한다. 또한, DC-DC Converter에 이 기법이 적용되었을 때의 효과와 이 결과가 RF Receiver system에 미치는 효과를 Noise 측면에서 연구하였다. 제안하는 Relaxation Oscillator 출력 중심주파수는 7.9 MHz이고, 온도보상기법을 적용하여 온도변화에 따라 주파수가 보상되도록 설계하였다. 이 칩은 $0.18{\mu}m$ 공정으로 설계하였고, 칩의 면적은 $220{\mu}m{\times}280{\mu}m$이다. 전류 소모는 공급전압인 1.8 V에서 $500{\mu}A$이다.