• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.922-929
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• 2005

This paper proposes an adaptive pilot beacon equipment for mobile communication systems based on direct spread spectrum technology which generates the pilot channel for handoff between base stations by using the information acquired from the downstream wireless signal regarding the overhead channel information. Such an adaptive pilot beacon equipment will enable low power operation since among the wireless signals, only the pilot channel will be generated and transmitted. The pilot channel in the downstream link of the CDMA receiver is used to acquire time and frequency synchronization and this is used to calibrate the offset for the beacon, which implies that time synchronization using GPS is not required and any location where forward receive signal can be received can be used as the installation site. The downstream link pilot signal searching within the CDMA receiver is performed by FPGA and DSP. The FPGA is used to perform the initial synchronization for the pilot searcher and DSP is used to perform the offset correction between beacon clock and base station clock. The CDMA transmitter the adaptive pilot beacon equipment will use the timing offset information in the pilot channel acquired from the CDMA receiver and generate the downstream link pilot signal synchronized to the base station. The intermediate frequency signal is passed through the FIR filter and subsequently upconverted and amplified before being radiated through the antenna.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.