• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.52-53
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• 2012

This paper presents a new control scheme for a three-phase split DC-link capacitor inverter as an AC power supplies. The proposed control method can maintain the balanced sinusoidal output voltage under unbalanced and nonlinear load conditions. The validity of the control method has been verified by simulation results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.9-11
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• 2018

본 논문은 넓은 영전압 스위칭 범위와 고효율을 가지는 Split-Capacitor Dual-Active-Bridge 컨버터를 제안한다. 제안한 컨버터는 기존의 Dual-Active-Bridge의 풀-브릿지 구조를 Split-Capacitor 구조로 변경하여 회로를 개선하였다. 비록 제안한 컨버터는 변압기 전류가 기존의 회로보다 2배만큼 높아지지만 6개 스위치의 정격 전압이 절반으로 줄어들며, 넓은 영전압 스위칭 범위를 가진다. 또한 변압기 전류의 증가로 인해, 기존의 컨버터에 비해 1/4만큼 작은 누설 인덕턴스로 같은 전력을 넘길 수 있다. 추가된 커패시터는 변압기 DC 성분에 의한 포화 문제를 막아주며 두 개의 출력을 가질 수 있도록 한다. 제안한 컨버터의 성능을 검증하기 위해 3-kW의 시제품을 제작하여 실험을 통해 증명하였다.

• 전력전자학회논문지
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• 제23권5호
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• pp.352-358
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• 2018

A split-capacitor (SC) dual-active-bridge (DAB) converter is proposed in this study. The DC-link capacitors of input and output are split in the proposed converter. The primary and secondary windings of transformer are connected to the midpoints of the DC-links. Hence, the SC DAB converter can inherently prevent transformer from saturation. Although the switch current stress of the proposed converter is twice that of the conventional DAB converter, the switch voltage stress is reduced by half. Therefore, the proposed converter can reduce switching loss and achieve high efficiency in a high switching frequency. Given the SC structure, the proposed converter can readily be connected to neutral-point-clamped- or half-bridge-type converters. The topology of the proposed converter is presented and the operating principle is analyzed in detail. A 3-kW hardware prototype was built and tested to verify the performance of the proposed converter.

• Journal of Power Electronics
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• 제18권6호
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• pp.1720-1728
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• 2018

This paper proposes a novel soft starting algorithm by using PWM inverter technique to control an amplitude of the motor starting current at a single-phase induction motor (SPIM). Traditional SPIM starting methods such as a Split-Phase, Capacitor-Start, Permanent-Split Capacitor (PSC), Capacitor-Start Capacitor-Run (CSCR), basically cannot control the magnitude of starting current due to the fixed system structures. Therefore, in this paper, a soft starting algorithm based on a proportional resonant (PR) control with a variable and constant frequency is proposed to reduce the inrush current and starting up time. In addition, a transition algorithm for operation modes is devised to generate a constant voltage and constant frequency (CVCF). The validity and effectiveness of the proposed soft starting method and transition algorithm are verified through experimental results.

• Journal of Power Electronics
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• 제16권5호
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• pp.1928-1938
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• 2016

The three-phase four-wire shunt active power filter (APF) is an effective method to solve the harmonic problem in three-phase four-wire power systems. In addition, it has two possible topologies, a four-leg inverter and a three-leg inverter with a split-capacitor. There are some studies investigating DC-link voltage control in three-phase four-wire APFs. However, when compared to the four-leg inverter topology, maintaining the balance between the DC-link upper and lower capacitor voltages becomes a unique problem in the three-leg inverter with a split-capacitor topology, and previous studies seldom pay attention to this fact. In this paper, the influence of the balance between the two DC-link voltages on the compensation performance, and the influence of the voltage balance controller on the compensation performance, are analyzed. To achieve the balance between the two DC-link capacitor voltages, and to avoid the adverse effect the voltage balance controller has on the APF compensation performance, a new DC-link voltage balance control strategy for the three-phase four-wire split-capacitor APF is proposed. Representative simulation and experimental results are presented to verify the analysis and the proposed DC-link voltage balance control strategy.

• 대한전자공학회논문지SD
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• 제47권6호
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• pp.43-50
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• 2010

본 논문에서는 시스템 모듈에서 발생하는 EMI를 줄이기 위해 분할된 전원/접지 평판 구조에 의해 발생하는 방사성 방출(Radiated emission)을 분석하였다. 분석을 위해 다양한 조건을 갖는 시험 기판(Test board)에 대한 자기장과 전기장을 시뮬레이션하고 측정하여 비교하였다. 이 분석 결과는 입력 신호의 주파수 대역에서 반사계수의 위상이 $0^{\circ}$에 근접하도록 하며, 입력 신호의 주파수와 분할된 전원/접지 평판 구조의 공진주파수가 일치하지 않도록 분할된 접지 갭의 폭과 위치를 결정함으로써 방사성 방출을 줄일 수 있음을 보여준다. 또한, 스티칭 커패시터(Stitching capacitor)를 사용하여 방사성 방출을 저감시킬 수 있으며, 방사성 방출을 효과적으로 저감시키기 위해 입력 신호의 주파수에서 반사계수의 크기를 낮추고 위상이 $0^{\circ}$에 근접하도록 스티칭 커패시터의 값과 위치를 결정할 필요가 있음을 알 수 있다.

• 전기의세계
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• 제31권2호
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• pp.132-140
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• 1982

Designing the capacitor-run motor for balanced operation is accompanied with the excessive capacitor value and low capacitor terminal voltage of condenser. As a solution for this problems, It was reported the design by equal volt-ampere method. The running characteristics of capacitor-run motor by this method due to the balancing point selection, however, has a room to be studied further. This paper deals with the determination of the winding ratio and capacitor value of a permarient-split capacitor motor by balanced operation and equal volt-ampere method at the different load points. The analysis of the running characteristics of a motor and its designing method also presented for both cases. It concluded that the running characteristics due to the equal volt-ampere operation are very close to the balanced operation.

• 한국정보통신학회논문지
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• 제7권8호
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• pp.1751-1758
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• 2003

본 논문에서는 V55 마이크로프로세서로 제어되는 반브릿지 인버터를 사용하여 영구 콘덴서형 단상유도 전동기의 가변속 구동에 대해 연구하였다. Patel의 알고리즘을 이용한 SHE(Selected Harmonic Elimination) PWM 구동방식에 의한 V/F 제어로 출력전압의 고조파분을 제거할 수 있으며, 속도의 제어 범위가 넓어짐을 알 수 있었다. 제안한 방법을 시뮬레이션과 실험의 결과로 입증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.884-885
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• 2007

This paper presents an window based user-friendly designed characteristics analysis program of permanent-split capacitor single-phase induction motor. For the analysis, equivalent magnetic circuit and symmetrical coordinate method are used. The saturation effect and iron loss of stator and rotor core are considered. The analysis program is made to GUI type which can be used easily by many elementary designer. The accuracy of analysis is verified by comparison with experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.108-113
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• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.