• 제목/요약/키워드: Spectre

검색결과 76건 처리시간 0.029초

802.11n WLAN용 ${\Delta}{\Sigma}$ Fractional-N 주파수 합성기의 피드백 체인 설계 (A Design of ${\Delta}{\Sigma}$ Fractional-N Frequency Synthesizer Using Pulse Removed PFD for 802.11 n Standard)

  • 전부원;김종철;노형환;박준석;오하령;성영락;정명섭
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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    • pp.161-162
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    • 2008
  • 본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed RFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블록은 Cadence spectre를 이용하여 검증하였다.

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Touch Screen Sensing Circuit with Rotating Auto-Zeroing Offset Cancellation

  • Won, Dong-Min;Kim, HyungWon
    • Journal of information and communication convergence engineering
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    • 제13권3호
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    • pp.189-196
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    • 2015
  • In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

Low-Power Receiver Circuit for Wireless Communication System

  • Morijiri, Keiji;Yazaki, Toru;Yamamoto, Hiroya;Hyogo, Akira;Sekine, Keitaro
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -2
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    • pp.1192-1195
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    • 2002
  • In this paper, we propose Low-Power Receiver circuits for a wireless communication system using ASK signal. Their structures are suitable for low supply current. The proposed circuits are designed and simulated by Spectre using 0.8m CMOS process parameters, and operate with supply current below 1.5${\mu}\textrm{A}$.

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Behavioral Current-Voltage Model with Intermediate States for Unipolar Resistive Memories

  • Kim, Young Su;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권6호
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    • pp.539-545
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    • 2013
  • In this paper, a behavioral current-voltage model with intermediate states is proposed for analog applications of unipolar resistive memories, where intermediate resistance values between SET and RESET state are used to store analog data. In this model, SET and RESET behaviors are unified into one equation by the blending function and the percentage volume fraction of each region is modeled by the Johnson-Mehl-Avrami (JMA) equation that can describe the time-dependent phase transformation of unipolar memory. The proposed model is verified by the measured results of $TiO_2$ unipolar memory and tested by the SPECTRE circuit simulation with CMOS read and write circuits for unipolar resistive memories. With the proposed model, we also show that the behavioral model that combines the blending equation and JMA kinetics can universally describe not only unipolar memories but also bipolar ones. This universal behavioral model can be useful in practical applications, where various kinds of both unipolar and bipolar memories are being intensively studied, regardless of polarity of resistive memories.

자동차용 고출력 전압모드 벅컨버터 IC (A High-Power Voltage Mode Buck Converter IC for Automotive Applications)

  • 박현일;서민성;박시홍
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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    • pp.83-84
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    • 2009
  • This paper presents a step-down converter IC for automotive applications. This device was designed for a 40V/1A high-power output for voltage reference of automotive IC. It provides 250kHz PWM(pulse width modulation) and PFM(pulse frequency modulation) according to load conditions. This device was simulated Spectre of IC Design Tool And fabricated Dong-bu Hitec 0.35um BD350BA process.

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광대역 전디지털 클록 데이터 복원회로 설계 (Design of Wide-range All Digital Clock and Data Recovery Circuit)

  • 고귀한;정기상;김강직;조성익
    • 전기학회논문지
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    • 제61권11호
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    • pp.1695-1699
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    • 2012
  • This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

Pulse Removed PFD를 이용한 802.11n WLAN용 ${\Delta}{\Sigma}$ Fractional-N 주파수 합성기 설계 (A Design of ${\Delta}{\Sigma}$ Fractional-N Frequency Synthesizer Using Pulse Removed PFD for 802.11n Standard)

  • 김종철;전부원;노형환;박준석;오하령;성영락;정명섭
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.1386-1388
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    • 2008
  • 본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed PFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블락은 Cadence spectre 를 이용하여 검증하였다.

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톱니파를 이용한 플라이백 컨버터의 일차 측 제어 (Primary side control of Flyback converter using sawtooth wave)

  • 남상국;김기현;김민성;서길수;김남균;송한정
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2015년도 제46회 하계학술대회
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    • pp.932-933
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    • 2015
  • This paper presents methods to achieve and control accurate output voltage. PSR removed secondary output voltage sensing circuit, therefore standby power loss can be decreased. When sensing the auxiliary winding voltage, sensing must be done at accurate branch which has $V_O$ information. For this reason this paper presents the PSR sensing technique using sawtooth wave and peak detector. Circuit verification carried out with Spectre in Cadence corporation and Manga/Hynix $0.35{\mu}m$ 700V process.

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Physicochemical Changes in UV-Exposed Low-Density Polyethylene Films

  • Salem, M.A.;Farouk, H.;Kashif, I.
    • Macromolecular Research
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    • 제10권3호
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    • pp.168-173
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    • 2002
  • Unstabilized low-density polyethylene (LDPE) films and films formulated with hindered amine light stabilizer (HALS) were exposed to UV-radiation; and the physicochemical changes during photooxidation processes have been investigated using tensile, FTIR spectre-photometric and thermal analytical (DSC) techniques. The dependence of tensile properties (elongation- and stress-at-break), carboxyl index and heat of fusion on UV-irradiation time have been discussed. The use of HALS is found to be effective in maintaining the UV-mechanical properties of the LDPE films. The experimental results showed that there exists no correlation between mechanical properties and carbonyl index, whereas crystallinity correlates well with carbonyl index in unstabilized and stabilized films for irradiation times greater than 100 h. The rate of formation of carbonyl groups is found to be dependent on UV exposure time. Crystallinity of the film samples is strongly influenced by both exposure time and presence of HALS.

Fractional-N 주파수 합성기를 위한 위상 잡음 특성이 개선된 전압 제어 발진기 (Optimized Voltage Controlled Oscillator(VCO) for Fractional-N Frequency Synthesizer)

  • 안진오;서우형;김인정;김대정
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.519-520
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    • 2006
  • In this paper, we propose a voltage-controlled ring oscillator (VCO) for a 900 MHz low-noise fractional-N frequency synthesizer. The VCO delay cell is based on an nMOS source-coupled pair with load elements [1] and a combined tail current sources which consist of a large and a small current source to control the integer and fractional behaviors, respectively. The Spectre simulation results of the scheme in a 0.18um CMOS process show the accurate control of the KVCO better than the conventional one.

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