• Journal of information and communication convergence engineering
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• v.17 no.1
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• pp.1-7
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• 2019

In this paper, we present the block diagonalization (BD) algorithm for the multiple-user multiple input multiple output (MU-MIMO) $4{\times}4$ system using specific purpose processor (SPP) hardware. Our objective is to improve the single-user MIMO (SU-MIMO) system using the MU-MIMO technology, which is remarkably fast and allows more users to connect simultaneously. To that end, our MU-MIMO precoder uses the BD algorithm to ensure signal integrity when connecting multiple users; but remains accurate and stable. However, a precoder that uses the BD algorithm is computationally complex; therefore, we use an SPP with special functions designed to compute the BD algorithm. The implementation test results show that our SPP computes the BD algorithm faster than the software solution.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.775-787
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• 2010

Unlike general-purpose CPUs, the GPUs have been specialized as many-core streaming processors, and are frequently replacing the CPUs in an increasing range of computations thanks to their outstanding parallel computing capacity. In order to respond to such trend, NVIDIA has recently issued a new parallel computing architecture called CUDA(Compute Unified Device Architecture), offering a flexible GPU programming environment for GPGPU(General Purpose GPU) computing. In general, when programmers use the CUDA API, they should clearly understand many aspects of GPU's computing architecture to produce efficient parallel software. In this article, we explain several optimization techniques for CUDA programming that we have verified through a lot of experiment and trial and error, and review how those techniques affect the performance of code execution. In particular, we use a specific problem as an example to analyze several elements that affect performances, such as effective accesses to hierarchical memory system, processor occupancy, and latency hiding. In conclusion, we present several directions that may be utilized effectively in CUDA-based parallel programming.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.189-198
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• 2015

Most IoT-related approaches have tried to establish the relation by connecting the network between things. The proposed research will present how the pervasive interaction of eco-system formed by touching the objects between humans and things can be recognized on purpose. By collecting and sharing the detected patterns among all kinds of things, we can construct the environment which enables individualized interactions of different objects. To perform the aforementioned, we are going to utilize technical procedures such as event-driven signal processing, pattern matching for signal recognition, and hardware in the loop simulation. We will also aim to implement the prototype of sensor processor based on Arduino MCU, which can be integrated with system using Arduino-Matlab/Simulink hybrid-interoperation environment. In the experiment, we use piezo transducer to detect the vibration or vibrates the surface using acoustic wave, which has specific frequency spectrum and individualized signal shape in terms of time axis. The signal distortion in time and frequency domain is recorded into memory tracer within sensor processor to extract the meaningful pattern by comparing the stored with lookup table(LUT). In this paper, we will contribute the initial prototypes for the acoustic touch processor by using off-the-shelf MCU and the integrated framework based on Matlab/Simulink model to provide the individualization of the touch-sensing for the user on purpose.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.539-548
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• 2015

In this paper, shared memory feature was developed in multi-core system with different OS for different processor-specific bus, while conducting an experiment on shared memory feature between the two processors based on embedded Linux system. For the purpose of developing shared memory in dual bus structure, memory controller was used, while managing shared memory segment through list data structure. For AMP multi-core test, Linux OS was installed in 2 processor cores. In addition, it verified the creation and use of shared memory by using kernel module implemented to test shared memory.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.72-82
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• 2002

This paper presents the design technology of a Graphic Generator which drives the embedded aircraft display equipments such as HUD(Head-Up Display) and MFD (Multi-Function Display) those provide pilot with the most important mission information. The main issue of this design is how we can implement the real-time embedded graphic generator using a general purpose processor as a substitute for the obsolete the production of specific graphic processor in the military market. So we proposed two kinds of method that one is a software solution so called graphic kernel system, interpreting the display file, controlling the graphic system and pre-processing graphic primitives, the other is a hardware solution so called graphic engine, interpreting passed commands through the graphic kernel system, post-processing the looping calculation taking much of time as implemented by software. We have tested and verified the functionalities and the required performance of Graphic Generator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.939-946
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• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.96-102
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• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• Korean Management Science Review
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• v.11 no.2
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• pp.1-27
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• 1994

A reliability data processing MPRDP (Multi-Purpose Reliability Data Processor) has been developed in FORTRAN language since Jan. 1992 at KAERI (Korean Atomic Energy Research Institute). The purpose of the research is to construct a reliability database(plant-specific as well as generic) by processing various kinds of reliability data in most objective and systematic fashion. To account for generic estimates in various compendia as well as generic plants' operating experience, we developed a 'three-stage' Bayesian procedure[1] by logically combining the 'two-stage' procedure[2] and the idea for processing generic estimates[3]. The first stage manipulates generic plant data to determine a set of estimates for generic parameters,e.g. the mean and the error factor, which accordingly defines a generic failure rate distribution. Then the second stage combines these estimates with the other ones proposed by various generic compendia (we call these generic book type data). This stage adopts another Bayesian procedure to determine the final generic failure rate distribution which is to be used as a priori distribution in the third stage. Then the third stage updates the generic distribution by plant-specific data resulting in a posterior failure rate distribution. Both running failure and demand failure data can be handled in this code. In accordance with the growing needs for a consistent and well-structured reliability database, we constructed a generic reliability database by the MPRDP code[4]. About 30 generic data sources were reviewed and available data were collected and screened from them. We processed reliability data for about 100 safety related components frequently modeled in PSA. The underlying distribution for the failure rate was assumed to be lognormal or gamma, according to the PSA convention. The dependencies among the generic sources were not considered at this time. This problem will be approached in further study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1490-1494
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• 2006

Most network equipment is an embedded system designed to execute specific function. An embedded system is an electronic control system mixing hardware and software to execute only fixed function for the purpose of system, not confuter, performing diverse function for a wide use. Early embedded system executed only simple function, combining specific function with optimization, a micro size, and low power, but it has developed to meet complex and diverse system. The purpose of this study is to realize DHCP server based on embedded system. To achieve this, embedded Linux was ported in ez Bord-M01 mounted with Intel Strong ARM SA1110 processor, and ethernet-based network was constructed for network function. In this way, this study suggests embedded DHCP server where Window and Linux client hosts are dynamically configurated as network information by dynamically assigning network information in embedded board.