• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.679-682
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• 2005

Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.3 no.1
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• pp.18-25
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• 1978

The 1/f noise spectrum of short-circuited output drain current due to the Shockley-Read-Hal] recombination centers with a single lifetime in homogeneous nondegenerate MOS-field effcte transtors with n-type channel is calculated under the assumptions that the quasi-Fermi level for the carriers in each energy band can not be defined if we include the fluctuation for time varying quantities. and so 1/f noise is a majority carrier effect. Under these assumptions the derived 1/f noise in this paper show some essential features of the 1/f noise in MOS-field effect transistors. That is, it has no lowfrequency plateau and is proportionnal to the channel cross area A and to the driain bias voltage Vd and inversely proportional to the channel length L3 in MOS field effect transistors. This model can explain the discrepancy between the transition frequency of the noise spectrum from 1/f- response to 1/f2 and the frequency corresponding to the relaxation time related to the surface centers in p-n junction diodes. In this paper the results show that the functional form of noise spectrum is greatly influenced by the functional forms of the electron capture probability cn (E) and the relaxation time r (E) for scattering and the case of lattice scattering show to be responsible for the 4 noise in MOS fold effect transistors. So we canconclude that the source of 1/f noise is due to lattice scattering.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.26 no.12
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• pp.605-619
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• 2014

This article reviews the papers published in the Korean Journal of Air-Conditioning and Refrigeration Engineering during 2013. It is intended to understand the status of current research in the areas of heating, cooling, ventilation, sanitation, and indoor environments of buildings and plant facilities. Conclusions are as follows. (1) The research works on the thermal and fluid engineering have been reviewed as groups of fluid machinery, pipes and relative parts including orifices, dampers and ducts, fuel cells and power plants, cooling and air-conditioning, heat and mass transfer, two phase flow, and the flow around buildings and structures. Research issues dealing with home appliances, flows around buildings, nuclear power plant, and manufacturing processes are newly added in thermal and fluid engineering research area. (2) Research works on heat transfer area have been reviewed in the categories of heat transfer characteristics, pool boiling and condensing heat transfer and industrial heat exchangers. Researches on heat transfer characteristics included the results for general analytical model for desiccant wheels, the effects of water absorption on the thermal conductivity of insulation materials, thermal properties of Octadecane/xGnP shape-stabilized phase change materials and $CO_2$ and $CO_2$-Hydrate mixture, effect of ground source heat pump system, the heat flux meter location for the performance test of a refrigerator vacuum insulation panel, a parallel flow evaporator for a heat pump dryer, the condensation risk assessment of vacuum multi-layer glass and triple glass, optimization of a forced convection type PCM refrigeration module, surface temperature sensor using fluorescent nanoporous thin film. In the area of pool boiling and condensing heat transfer, researches on ammonia inside horizontal smooth small tube, R1234yf on various enhanced surfaces, HFC32/HFC152a on a plain surface, spray cooling up to critical heat flux on a low-fin enhanced surface were actively carried out. In the area of industrial heat exchangers, researches on a fin tube type adsorber, the mass-transfer kinetics of a fin-tube-type adsorption bed, fin-and-tube heat exchangers having sine wave fins and oval tubes, louvered fin heat exchanger were performed. (3) In the field of refrigeration, studies are categorized into three groups namely refrigeration cycle, refrigerant and modeling and control. In the category of refrigeration cycle, studies were focused on the enhancement or optimization of experimental or commercial systems including a R410a VRF(Various Refrigerant Flow) heat pump, a R134a 2-stage screw heat pump and a R134a double-heat source automotive air-conditioner system. In the category of refrigerant, studies were carried out for the application of alternative refrigerants or refrigeration technologies including $CO_2$ water heaters, a R1234yf automotive air-conditioner, a R436b water cooler and a thermoelectric refrigerator. In the category of modeling and control, theoretical and experimental studies were carried out to predict the performance of various thermal and control systems including the long-term energy analysis of a geo-thermal heat pump system coupled to cast-in-place energy piles, the dynamic simulation of a water heater-coupled hybrid heat pump and the numerical simulation of an integral optimum regulating controller for a system heat pump. (4) In building mechanical system research fields, twenty one studies were conducted to achieve effective design of the mechanical systems, and also to maximize the energy efficiency of buildings. The topics of the studies included heating and cooling, HVAC system, ventilation, and renewable energies in the buildings. Proposed designs, performance tests using numerical methods and experiments provide useful information and key data which can improve the energy efficiency of the buildings. (5) The field of architectural environment is mostly focused on indoor environment and building energy. The main researches of indoor environment are related to infiltration, ventilation, leak flow and airtightness performance in residential building. The subjects of building energy are worked on energy saving, operation method and optimum operation of building energy systems. The remained studies are related to the special facility such as cleanroom, internet data center and biosafety laboratory. water supply and drain system, defining standard input variables of BIM (Building Information Modeling) for facility management system, estimating capability and providing operation guidelines of subway station as shelter for refuge and evaluation of pollutant emissions from furniture-like products.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.6
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• pp.1-6
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• 2011

A transparent oxide thin film transistors (Transparent Oxide-TFT) have been fabricated by RF magnetron sputtering at room temperature using amorphous indium zinc oxide (a-IZO) as both of active channel and source/drain, gate electrodes and co-sputtered $HfO_2-Al_2O_3$ (HfAIO) as gate dielectric. In spite of its high dielectric constant > 20), $HfO_2$ has some drawbacks including high leakage current and rough surface morphologies originated from small energy band gap (5.31eV) and microcrystalline structure. In this work, the incorporation of $Al_2O_3$ into $HfO_2$ was obtained by co-sputtering of $HfO_2$ and $Al_2O_3$ without any intentional substrate heating and its structural and electrical properties were investigated by x-ray diffraction (XRD), atomic force microscopy (AFM) and spectroscopic ellipsometer (SE) analyses. The XRD studies confirmed that the microcrystalline structures of $HfO_2$ were transformed to amorphous structures of HfAIO. By AFM analysis, HfAIO films (0.490nm) were considerably smoother than $HfO_2$ films (2.979nm) due to their amorphous structure. The energy band gap ($E_g$) deduced by spectroscopic ellipsometer was increased from 5.17eV ($HfO_2$) to 5.42eV (HfAIO). The electrical performances of TFTs which are made of well-controlled active/electrode IZO materials and co-sputtered HfAIO dielectric material, exhibited a field effect mobility of more than $10cm^2/V{\cdot}s$, a threshold voltage of ~2 V, an $I_{on/off}$ ratio of > $10^5$, and a max on-current of > 2 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.