• 제목/요약/키워드: Solid State Drive

검색결과 119건 처리시간 0.033초

Development of a Novel 30 kV Solid-state Switch for Damped Oscillating Voltage Testing System

  • Hou, Zhe;Li, Hongjie;Li, Jing;Ji, Shengchang;Huang, Chenxi
    • Journal of Power Electronics
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    • 제16권2호
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    • pp.786-797
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    • 2016
  • This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

SSD 수명 관점에서 리눅스 I/O 스택에 대한 실험적 분석 (An Empirical Study on Linux I/O stack for the Lifetime of SSD Perspective)

  • 정남기;한태희
    • 전자공학회논문지
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    • 제52권9호
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    • pp.54-62
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    • 2015
  • 낸드 플래시 기반의 SSD (Solid-State Drive)는 HDD (Hard Disk Drive) 대비 월등한 성능에도 불구하고 쓰기 회수 제한이라는 태생적 단점을 가지고 있다. 이로 인해 SSD의 수명은 워크로드에 의해 결정되어 SSD의 기술 변화 추세인 SLC (Single Level Cell) 에서 MLC (Multi Level Cell) 로의 전환, MLC에서 TLC (Triple Level Cell) 로의 전환에 있어 큰 도전이 될 수 있다. 기존 연구들은 주로 wear-leveling 또는 하드웨어 아키텍처 측면에서 SSD의 수명 개선을 다루었으나, 본 논문에서는 호스트가 요청한 쓰기에 대해 SSD가 낸드플래시 메모리를 통해 처리하는 수명관점의 효율성을 대변하는 WAF (Write Amplification Factor) 관점에서 Host I/O 스택 중 파일 시스템, I/O 스케줄러, 링크 전력에 대해 JEDEC 엔터프라이즈 워크로드를 이용해 I/O 스택 최적 구성에 대해 실험적 분석을 수행하였다. WAF는 SSD의 FTL의 효율성을 측정하는 지표로 수명관점에서 가장 객관적으로 사용한다. I/O 스택에 대한 수명 관점의 최적 구성은 MinPower-Dead-XFS로 최대 성능 조합인 MaxPower-Cfq-Ext4에 비해 성능은 13% 감소하였지만 수명은 2.6 배 연장됨을 확인하였다. 이는 I/O 스택의 최적화 구성에 있어, SSD 성능 관점뿐만 아니라 수명 관점의 고려에 대한 유의미를 입증한다.

SSD 기반의 가상메모리 시스템을 위한 상태기반 페이지 할당 기법 (SAPA : State-Aware Page Allocation Scheme for SSD Based Virtual Memory Systems)

  • 김현욱;안우현
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2011년도 한국컴퓨터종합학술대회논문집 Vol.38 No.1(B)
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    • pp.438-441
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    • 2011
  • 최근 태블릿 컴퓨터(Tablet computer) 등 첨단 모바일 기기가 대중화되고 고성능 노트북이 널리 사용되면서 SSD(Solid State Drive)를 주 저장장치로 사용하는 시스템이 증가하고 있다. 이들 시스템에서는 SSD를 가상메모리의 스왑 영역으로 사용하므로 이에 적합한 가상메모리 정책이 필요하다. SSD 제조사는 SSD 내부의 자세한 정보는 제공하지 않기 때문에 최적화된 할당에 어려움이 생긴다. 본 논문에서는 SSD의 내부 상태를 기록하고, VM의 스왑 공간으로 사용 시 각블록 상태를 고려하여 최적화된 할당 페이지를 선택하는 기법을 제안한다.

반도체 소자기반 펄스 전원용 게이트 구동 및 시험회로 설계 (Design of gate driver and test circuits for solid-state pulsed power modulator)

  • 공지웅;옥승복;안석호;장성록;류홍제
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2012년도 전력전자학술대회 논문집
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    • pp.230-231
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    • 2012
  • This paper describes a gate driver that operates numerous semiconductor switch in the solide-state pulsed power modulator. the proposed gate driver is designed to receive both the isolated drive-power and the on/off pulse signals through the transformer. Moreover, the IGBT-switch can be quickly turned off by adding protection circuit. Therefore it protects the IGBT-switch from the arc condition that frequently occurs in high-voltage pulse application. To comprehend operating characteristic of each IGBT-switch in pulse output condition, the device consisting of a high efficiency soft-switching capacitor charger and two series stacking IGBT-switch is developed. Finally, the relability of the proposed gate driver and the device for its test are proved through PSpice simulation and experiments.

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마이크로프로세서를 이용한 3상 브리지 콘버터의 제어회로 설계에 관한 연구 (A Study on the Design of a Control Circuit for Three- Phase Full Bridge Converter Using Microprocessor)

  • 노창주;김윤식;김영길;유진열;류승각
    • Journal of Advanced Marine Engineering and Technology
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    • 제16권4호
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    • pp.102-112
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    • 1992
  • The three-phase full(6-pulse) bridge controlled rectifier is one of the most widely used types of solid-state converters in DC drive applications for higher performance. In most of the previous designs, the gate control circuits of the converter have been designed with analog method which can be easily affected by noise. Nowdays with advances of microelectronics and power electronics, microprocessor and pheripal LSIs are increasingly used for eliminating this problems. In this paper, a novel general-purpose microprocessor -based firing system and control scheme for a three-phase controlled rectifier bridge has been developed and tested. Using the phase relations between ${\Delta}$-Y transformer in power operation part, gate pulse of the converter is generated with real time process so that microprocessor may share its time to control algorithms efficiently. The firing angle of the converter is smoothly controlled in the range of 0 $^{\dirc}$ to 180$^{\dirc}$ with a fast respone and a constant open loop gain, even for the case where the converter is fed by a weak AC system of unregulated frequency. The hardware and software control circuit implementation built around a 80286 microprocessor is discussed, and the experimental results are given. This scheme uses less hardware components and has higher dynamic performance in variable speed DC drive applications.

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인공위성 중계기용 고출력 전력증폭기의 구현에 관한 연구 (A Study on the solid-state power amplifier for satehite transponders)

  • 김대현;여인혁;이두한;홍의석
    • 한국통신학회논문지
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    • 제19권11호
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    • pp.2228-2237
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    • 1994
  • This paper describes the development of a Ku-band ($12.25GHz\sim12.75GHz$) SSPA intended as a replacement for TWTAs used in communication satelite transponder. The power stage of the amplifier consists of tow intrmally matched 8W FET divices combined using the branch-line coupler. To operate this stage, the drive stage has been designed with intermally matched 2W, 4W, 8W FET and two medium power FETs. The entire amplifier is made up by a aluminum chassis housing both the RF circuit and the bias circuitry. A regrlator/sequencing circuitry is used for FET biasing. The amplifier results implemented in this way show $41\pm0.3dB$ small-signal gain, 15W saturation power, a typical two tone $IM_3=-21.5dBc$ with single carrier backed off 5dB from saturation, $2^*/dBmax$ AM/PM conversion, and $3.47\pm0.25nsec$ group delay.

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SSD 가비지 콜렉션 비용을 줄이는 효율적인 적시 캐시 방출 기법 (In-Time Cache Eviction To Reduce Inefficient SSD Garbage Collection)

  • 김경민;하란
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2012년도 한국컴퓨터종합학술대회논문집 Vol.39 No.1(A)
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    • pp.349-351
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    • 2012
  • 낸드 플래시 메모리에서 가비지 콜렉션은 블록의 유효한 데이터들을 새로운 블록으로 옮기고 오래된 블록을 지우는 과정이다. 가비지 콜렉션에 의해 옮겨지는 페이지들은 작업의 양과 형태에 따라 오랫동안 유효한 페이지로 존재하기도 하고 그렇지 않은 경우도 있다. 본 논문에서는 반도체 디스크(Solid State Drive, 이하 SSD)에서 가비지 콜렉션이 비효율적으로 일어나는 경우를 정의하고 비효율적 가비지 콜렉션 과정으로 인한 비용을 줄이는 캐시 방출 기법을 소개한다. 이 기법을 시뮬레이션 해본 결과 작업 형태가 순차적일 때 LRU 캐시 알고리즘과 같이 사용되면 가비지 콜렉션에 의해 옮겨지는 페이지를 12%, 전체 쓰기 연산 횟수를 9%까지 줄일 수 있었고 블록 단위 LRU 알고리즘과 사용했을 때도 보다 좋은 성능을 보였다.

마이크로프로세서를 이용한 3상 브리지 콘버터의 제어회로 설계에 관한 연구 (A Study on the Design of a Control Circuit for Three-Phase Full Bridge Converter Using Microprocessor)

  • 노창주;김윤식;김영길;유진열;류승각
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1992년도 하계학술대회 논문집 B
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    • pp.985-987
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    • 1992
  • The three-phase full(6-pulse) bridge controlled rectifier is one of the most widely used types of solid-state converters in DC drive applications for higher performance. In most of the previous designs gate control circuits of the converter have been designed with analog method, whitch can be easily affected by noise. In this study microprocessor and pheripal LSIs are used for eliminating these problems and successful results have been obtained.

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Divided Disk Cache and SSD FTL for Improving Performance in Storage

  • Park, Jung Kyu;Lee, Jun-yong;Noh, Sam H.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권1호
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    • pp.15-22
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    • 2017
  • Although there are many efficient techniques to minimize the speed gap between processor and the memory, it remains a bottleneck for various commercial implementations. Since secondary memory technologies are much slower than main memory, it is challenging to match memory speed to the processor. Usually, hard disk drives include semiconductor caches to improve their performance. A hit in the disk cache eliminates the mechanical seek time and rotational latency. To further improve performance a divided disk cache, subdivided between metadata and data, has been proposed previously. We propose a new algorithm to apply the SSD that is flash memory-based solid state drive by applying FTL. First, this paper evaluates the performance of such a disk cache via simulations using DiskSim. Then, we perform an experiment to evaluate the performance of the proposed algorithm.

Performance Evaluation of a RAM based Storage System NGS

  • Kang, Yun-Hee;Kung, Jae-Ha;Cheong, Seung-Kook
    • International Journal of Contents
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    • 제5권4호
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    • pp.75-80
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    • 2009
  • Recently high-speed memory array based on RAM, which is a type of solid-state drive (SSD), has been introduced to handle the input/output (I/O) bottleneck. But there are only a few performance studies on RAM based SSD storage with regard to diverse workloads. In this paper, we focus on the file system for RAM based memory array based NGS (Next Generation Storage) system which is running on Linux operating system. Then we perform benchmark tests on practical file systems including Ext3, ReiserFS, XFS. The result shows XFS significantly outperforms other file systems in tests that represent the storage and data requests typically made by enterprise applications in many aspects. The experiment is used to design the dedicated file system for NGS system. The results presented here can help enterprises improve their performance significantly.