• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.54-62
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• 2015

Although NAND flash-based SSD (Solid-State Drive) provides superior performance in comparison to HDD (Hard Disk Drive), it has a major drawback in write endurance. As a result, the lifetime of SSD is determined by the workload and thus it becomes a big challenge in current technology trend of such as the shifting from SLC (Single Level Cell) to MLC (Multi Level cell) and even TLC (Triple Level Cell). Most previous studies have dealt with wear-leveling or improving SSD lifetime regarding hardware architecture. In this paper, we propose the optimal configuration of host I/O stack focusing on file system, I/O scheduler, and link power management using JEDEC enterprise workloads in terms of WAF (Write Amplification Factor) which represents the efficiency perspective of SSD life time especially for host write processing into flash memory. Experimental analysis shows that the optimum configuration of I/O stack for the perspective of SSD lifetime is MinPower-Dead-XFS which prolongs the lifetime of SSD approximately 2.6 times in comparison with MaxPower-Cfq-Ext4, the best performance combination. Though the performance was reduced by 13%, this contributions demonstrates a considerable aspect of SSD lifetime in relation to I/O stack optimization.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.438-441
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• 2011

최근 태블릿 컴퓨터(Tablet computer) 등 첨단 모바일 기기가 대중화되고 고성능 노트북이 널리 사용되면서 SSD(Solid State Drive)를 주 저장장치로 사용하는 시스템이 증가하고 있다. 이들 시스템에서는 SSD를 가상메모리의 스왑 영역으로 사용하므로 이에 적합한 가상메모리 정책이 필요하다. SSD 제조사는 SSD 내부의 자세한 정보는 제공하지 않기 때문에 최적화된 할당에 어려움이 생긴다. 본 논문에서는 SSD의 내부 상태를 기록하고, VM의 스왑 공간으로 사용 시 각블록 상태를 고려하여 최적화된 할당 페이지를 선택하는 기법을 제안한다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.230-231
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• 2012

This paper describes a gate driver that operates numerous semiconductor switch in the solide-state pulsed power modulator. the proposed gate driver is designed to receive both the isolated drive-power and the on/off pulse signals through the transformer. Moreover, the IGBT-switch can be quickly turned off by adding protection circuit. Therefore it protects the IGBT-switch from the arc condition that frequently occurs in high-voltage pulse application. To comprehend operating characteristic of each IGBT-switch in pulse output condition, the device consisting of a high efficiency soft-switching capacitor charger and two series stacking IGBT-switch is developed. Finally, the relability of the proposed gate driver and the device for its test are proved through PSpice simulation and experiments.

• Journal of Advanced Marine Engineering and Technology
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• v.16 no.4
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• pp.102-112
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• 1992

The three-phase full(6-pulse) bridge controlled rectifier is one of the most widely used types of solid-state converters in DC drive applications for higher performance. In most of the previous designs, the gate control circuits of the converter have been designed with analog method which can be easily affected by noise. Nowdays with advances of microelectronics and power electronics, microprocessor and pheripal LSIs are increasingly used for eliminating this problems. In this paper, a novel general-purpose microprocessor -based firing system and control scheme for a three-phase controlled rectifier bridge has been developed and tested. Using the phase relations between ${\Delta}$-Y transformer in power operation part, gate pulse of the converter is generated with real time process so that microprocessor may share its time to control algorithms efficiently. The firing angle of the converter is smoothly controlled in the range of 0 $^{\dirc}$ to 180$^{\dirc}$ with a fast respone and a constant open loop gain, even for the case where the converter is fed by a weak AC system of unregulated frequency. The hardware and software control circuit implementation built around a 80286 microprocessor is discussed, and the experimental results are given. This scheme uses less hardware components and has higher dynamic performance in variable speed DC drive applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2228-2237
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• 1994

This paper describes the development of a Ku-band ($12.25GHz\sim12.75GHz$) SSPA intended as a replacement for TWTAs used in communication satelite transponder. The power stage of the amplifier consists of tow intrmally matched 8W FET divices combined using the branch-line coupler. To operate this stage, the drive stage has been designed with intermally matched 2W, 4W, 8W FET and two medium power FETs. The entire amplifier is made up by a aluminum chassis housing both the RF circuit and the bias circuitry. A regrlator/sequencing circuitry is used for FET biasing. The amplifier results implemented in this way show $41\pm0.3dB$ small-signal gain, 15W saturation power, a typical two tone $IM_3=-21.5dBc$ with single carrier backed off 5dB from saturation, $2^*/dBmax$ AM/PM conversion, and $3.47\pm0.25nsec$ group delay.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.349-351
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• 2012

낸드 플래시 메모리에서 가비지 콜렉션은 블록의 유효한 데이터들을 새로운 블록으로 옮기고 오래된 블록을 지우는 과정이다. 가비지 콜렉션에 의해 옮겨지는 페이지들은 작업의 양과 형태에 따라 오랫동안 유효한 페이지로 존재하기도 하고 그렇지 않은 경우도 있다. 본 논문에서는 반도체 디스크(Solid State Drive, 이하 SSD)에서 가비지 콜렉션이 비효율적으로 일어나는 경우를 정의하고 비효율적 가비지 콜렉션 과정으로 인한 비용을 줄이는 캐시 방출 기법을 소개한다. 이 기법을 시뮬레이션 해본 결과 작업 형태가 순차적일 때 LRU 캐시 알고리즘과 같이 사용되면 가비지 콜렉션에 의해 옮겨지는 페이지를 12%, 전체 쓰기 연산 횟수를 9%까지 줄일 수 있었고 블록 단위 LRU 알고리즘과 사용했을 때도 보다 좋은 성능을 보였다.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.985-987
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• 1992

The three-phase full(6-pulse) bridge controlled rectifier is one of the most widely used types of solid-state converters in DC drive applications for higher performance. In most of the previous designs gate control circuits of the converter have been designed with analog method, whitch can be easily affected by noise. In this study microprocessor and pheripal LSIs are used for eliminating these problems and successful results have been obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.15-22
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• 2017

Although there are many efficient techniques to minimize the speed gap between processor and the memory, it remains a bottleneck for various commercial implementations. Since secondary memory technologies are much slower than main memory, it is challenging to match memory speed to the processor. Usually, hard disk drives include semiconductor caches to improve their performance. A hit in the disk cache eliminates the mechanical seek time and rotational latency. To further improve performance a divided disk cache, subdivided between metadata and data, has been proposed previously. We propose a new algorithm to apply the SSD that is flash memory-based solid state drive by applying FTL. First, this paper evaluates the performance of such a disk cache via simulations using DiskSim. Then, we perform an experiment to evaluate the performance of the proposed algorithm.

• International Journal of Contents
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• v.5 no.4
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• pp.75-80
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• 2009

Recently high-speed memory array based on RAM, which is a type of solid-state drive (SSD), has been introduced to handle the input/output (I/O) bottleneck. But there are only a few performance studies on RAM based SSD storage with regard to diverse workloads. In this paper, we focus on the file system for RAM based memory array based NGS (Next Generation Storage) system which is running on Linux operating system. Then we perform benchmark tests on practical file systems including Ext3, ReiserFS, XFS. The result shows XFS significantly outperforms other file systems in tests that represent the storage and data requests typically made by enterprise applications in many aspects. The experiment is used to design the dedicated file system for NGS system. The results presented here can help enterprises improve their performance significantly.