• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.329-331
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• 2006

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.221-223
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• 2006

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.71-76
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• 2012

SnBi 저온솔더의 플립칩 공정을 이용한 스마트 의류용 칩 접속공정에 대해 연구하였다. 캐리어 필름에 형성한 Cu 리드프레임을 $130^{\circ}C$에서 직물에 열압착 시킴으로써 Cu 리드프레임이 전사된 직물 기판을 형성하였다. 칩 시편에 SnBi 페이스트를 도포하여 솔더범프를 형성한 후 직물 기판의 Cu 리드프레임에 배열하고 $180^{\circ}C$에서 60초 동안 유지시켜 플립칩 본딩하였다. SnBi 저온솔더를 사용하여 형성된 스마트 의류용 플립칩 접속부의 평균 접속저항은 $9m{\Omega}$이었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 청정기술
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• 제17권4호
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• pp.306-313
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• 2011

인쇄회로기판(PCB)과 같은 전자부품을 제조시에 솔더링을 하기 위하여 플럭스나 솔더페이스트를 사용하며 솔더링 후에 부품에 잔류한 플럭스나 솔더페이스트를 제거하여야하는데 이것은 이들 물질이 잔류하였을 경우 부식이나 누전을 초래하여 부품의 성능을 떨어뜨리거나 고장을 일으킬 수 있다. 솔더링 후에 플럭스와 솔더플럭스 잔류물을 제거하기 위하여 오존파괴물질 세정제인 1,1,1-trichloroethane이나 HCFC-141b가 아직까지 많이 사용되고 있다. 본 연구에서는 이들 오존파괴성질을 가진 세정제를 대체하기 위하여 인화점이 존재하지 않는 비수계세정제를 개발하였고 산업현장 적용도 시도해 보았다. 인화점이 존재하지 않는 세정제를 개발하기 위해 탄화수소계 용제를 주 용제로 하고 글리콜에테르계, 에스테르계 및 불소계 용제를 첨가하여 비수계세정제를 배합하였고 이들의 물성 및 세정성을 평가하였다. 그리고 이들 배합세정제 중에 세정력이 뛰어난 세정제를 현장에 적용하여 보았다. 또한 배합된 비수계세정제의 사용후에 재활용 가능성을 평가하기 위하여 감압증류장치를 가동하여 사용 후의 세정제를 재활용시에 요구되는 운전 조건과 재활용율을 구하여 보았다. 배합세정제의 물성 측정 결과 모두 표면장력이 18.0~20.4 dyne/cm으로 비교적 낮았고 습윤지수도 비교적 높아 오염물에 대한 습윤력과 침투력이 우수할 것으로 기대되었고 불소계용제를 첨가하여 배합한 세정제는 인화성이 없음이 확인되어 사용하고 보관하기에 안전하리라 사료된다. 플럭스 및 솔더페이스트 세정 연구 실험 결과 대체목표세정제인 1,1,1-TCE와 HCFC-141b보다 세정력이 우수함을 확인할 수 있었다. 그리고 배합세정제 중에 우수한 세정제를 선정하여 HCFC-141b를 사용하는 산업현장의 PCB 세정에 적용한 결과 HCFC-141b보다 우수한 세정을 나타내어 산업현장에 적용 가능성을 보여 주었다. 또한 이들 제품을 감압증류장치를 이용하여 재활용 가능성을 평가 결과 운전조건 $100{\sim}110^{\circ}C$, 20~30 mbar에서 91.9~97.5%를 재활용할 수 있음을 보여주었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• Journal of Welding and Joining
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• 제29권5호
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• pp.95-98
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• 2011

Recently, there is a growing tendency that fine-pitch electronic devices are increased due to higher density and very large scale integration. Finer pitch printed circuit board(PCB) is to be decrease insulation resistance between circuit patterns and electrical components, which will induce to electrical short in electronic circuit by electrochemical migration when it exposes to long term in high temperature and high humidity. In this research, the effect of soldering flux acting as an electrical carrier between conductors on electrochemical migration was investigated. The PCB pad was coated with OSP finish. Sn3.0Ag0.5Cu solder paste was printed on the PCB circuit and then the coupon was treated by reflow process. Thereby, specimen for ion migration test was fabricated. Electrochemical migration test was conducted under the condition of DC 48 V, $85^{\circ}C$, and 85 % relative humidity. Their life time could be increased about 22% by means of removal of flux. The fundamentals and mechanism of electrochemical migration was discussed depending on the existence of flux residues after reflow process.

• ETRI Journal
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• 제41권3호
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• pp.396-407
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• 2019

Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.

• 센서학회지
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• 제5권5호
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• pp.21-29
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• 1996

(111), $n/n^{+}/n$ 3층 구조의 실리콘 기판을 HF 용액 내에서 양극반응시켜 선택확산된 $n^{+}$ 층에 다공질 실리콘층(Porous Silicon Layer : PSL)을 형성한 후, 이를 5% NaOH 수용액에서 식각하여 미세구조를 제조하는 다공질 실리콘 식각법을 이용한 실리콘 미세구조의 제조법으로 8개의 빔을 갖는 압저항형 실리콘 가속도센서를 제조하였다. 제조된 가속도센서의 매스 패드(mass pad)의 반경, 빔 길이, 빔 폭, 그리고 빔 두께는 각각 $700\;{\mu}m$, $50;{\mu}m$, $100\;{\mu}m$, $7\;{\mu}m$ 였다. 자동차의 응용을 위하여 50g 범위의 가속도를 측정할 수 있도록 진동질량은 2 mg으로 제조하였다. 이때, 진동질량을 부가하는 방법은 Pb/Sn/Ag 솔더 페이스트를 매스 패드에 디스펜싱한 후, 3-zone reflow 장치를 사용하여 열처리하였다. 제조된 가속도센서의 충격응답에 대한 감쇠시간은 약 30 ms로 나타났으며, 가산회로로 합한 출력의 감도는 2.9 mV/g이며, 비선형특성은 full scale 출력에서 2%이하로 측정되었다. 그리고 각 브릿지의 편차는 ${\pm}5%$ 미만으로 나타났다. 또한 측정된 타축감도는 약 4% 이하로 나타났으며, 시뮬레이션 결과로 부터 얻은 센서의 공진주파수는 2.15 KHz이었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.