• Smart Media Journal
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• v.11 no.11
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• pp.25-31
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• 2022

Deep learning-based image processing is essential for autonomous vehicles. To process road images in real-time in a System-on-Chip (SoC) environment, we need to execute deep learning models on a NPU (Neural Procesing Units) specialized for deep learning operations. In this study, we imported seven open-source image processing deep learning models, that were developed on GPU servers, to Texas Instrument Deep Learning (TIDL) NPU environment. We confirmed that the models imported in this study operate normally in the SoC virtual environment through performance evaluation and visualization. This paper introduces the problems that occurred during the migration process due to the limitations of NPU environment and how to solve them, and thereby, presents a reference case worth referring to for developers and researchers who want to port deep learning models to SoC environments.

• ETRI Journal
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• v.42 no.4
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• pp.480-490
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• 2020

More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.410-415
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• 2002

This paper describes the implementation of a SoC(System-on-a-Chip) and an ISDN communication terminal by the SoC in ISDN network. The SoC has been developed with the functions of 32-bit ARM7TDMI RISC core processor, network connection with S/T interface, TDM--bus interface and voice codec, user interface. And we also review the developed software structure and the ISDN service protocol procedures which are working on the SoC. And finally this paper describers a structure of an ISDN terminal equipment using the implemented SoC and terminal software.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.148-155
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• 2014

In this research a signal processing system is designed for detecting the ultrasonic signal envelope using Xilinx's Zynq SoC(system on chip). As a design tool, Vivado IDE(integrated design environment) is used to hierarchically design the whole signal processing system. The proposed system consists of a Zynq-internal ADC, an FIR(finite impulse response) BPF(band pass filter), an absolute value calculator, an FIR LPF(lpw pass filter), and the Kalman filter. Under this configuration, two design schemes, HW design scheme with LPF as a final stage and HW/SW co-design scheme with a Kalman filter as a final stage, are compared in terms of the performance and efficiency. As a result, envelope detecting performances of the two schemes are proved to be almost same, but the HW/SW co-design is verified to be much more efficient than the HW design considering the much smaller time consumption during system design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.39-46
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• 2005

This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.533-534
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• 2008

By using Dual Port DRAM to Multi-media SoC, an improved performance is achieved in this paper. The proposed scheme greatly help the multi-media SoC like a application for full HDTV, and it can be extended to the application field which is needed the low access latency with heavy traffic. Additionally, the proposed scheme help to down the BUM cost of system.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.5
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• pp.513-521
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• 2022

This study deals with an AI architecture model for collecting battlefield data using the tactical C4I system. Based on this model, the artificial staff can be utilized in tactical echelon. In the current structure of the Army's tactical C4I system, Servers are operated by brigade level and above and divided into an active and a standby server. In this C4I system structure, the AI server must also be installed in each unit and must be switched when the C4I server is switched. The tactical C4I system operates a server(DB) for each unit, so data matching is partially delayed or some data is not matched in the inter-working process between servers. To solve these issues, this study presents an operation concept so that all of alternate server can be integrated based on virtualization technology, which is used as an source data for AI Meta DB. In doing so, this study can provide criteria for the AI architectural model of the ground tactical echelon.

• Journal of the Korea Society for Simulation
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• v.27 no.1
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• pp.61-73
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• 2018

In the defense modeling and simulation, for the detailed analysis of the communication system, many studies have carried out the analysis under the C3 SoS(system of systems) which consists of C2(command and control) and C(communication). However, it requires time and space constraints of the C2 system. To solve this problem, this paper proposes a communication analysis method in the standalone system environment which is combined with the C system after abstracting the C2 system. In the abstraction process, we hypothesize the traffic model and mobility model for C system analysis and learn the parameters in the model based on machine learning. Through the proposed method, it is possible to construct traffic and mobility model with different output according to the battlefield. This case study shows how the process can be applied to the C3 SoS and the enhanced accuracy than the existing method. We expect that it is possible to carry out the efficient communication analysis against many experimental scenarios with various communication parameters.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.6
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• pp.278-285
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• 2006

Coating mixtures of the resin B-H for the application to the desulfurization system of power plant were coated on carbon steels and cured at the temperature of $65^{\circ}C{\sim}80^{\circ}C$. After being contacted with 70wt% $H_2SO_4$ solution of $100^{\circ}C\;and\;120^{\circ}C$ for several hours, their composition, Vicker's hardness and microstructures by SEM were examined. Corrosion resistance of the coating mixtures to $H_2SO_4$ solution was related to the content of $SO_3$ in the coated specimens after corrosion test. The lower curing temperature and the shorter curing time the coated specimens went through, the higher corrosion resistance to acid they showed, but the more cracks were developed at higher temperature. It was realized that the corrosion resistance to sulfaric acid solution was increased on the condition of curing temperature above $65^{\circ}C$ and curing time above 12 hours at least.