• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.8
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• pp.4227-4240
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• 2019

In this paper, we present our proposed magnetic induction based wireless communication system. The proposed system is designed to perform communication as well as distance measurement in underground environments. In order to improve the communication quality, we propose and implement the adaptive channel compensation technique. Based on the fact that the channel may be fast time-varying, we keep track of the channel status each time the data is received and accordingly compensate the channel coefficient for any change in the channel status. By using the proposed compensation technique, the developed platform can reliably communicate over distances of 10m while the packet error rate is being maintained under 5%. We also implement the distance measurement block that is useful for various applications that should promptly estimate the location of nearby nodes in communication. The distance between two nodes in communication is estimated by generating a table describing pairs of the magnetic signal strength and the corresponding distance. The experiment result shows that the platform can estimate the distance of a node located within 10m range with the measurement error less than 50cm.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.365-369
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• 2002

In this paper, DC motor controller has been designed by using SoC. SoC is short for System on a chip. This is a methodology that both a processor and some applications are integrated in a chip. In order to design this system based on SoC, PIC 16C57 has been selected as a processor because it has not too many instruction sets and simple data path named a harvard structure. And motor control module has been programmed by using VHDL. The advantages of the design based on SoC are as follows: simple structure, high speed working, easily verifying and simulating the system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1250-1256
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• 2017

In this research, a high-performance ultrasonic positioning system is proposed to track the positions of an indoor mobile object. Composed of an ultrasonic sender (mobile object) and a receiver (anchor), the system employs three ultrasonic time-off-flights (TOFs) and trilateration to estimate the positions of the object with an accuracy of sub-centimeter. On the other hand, because ultrasonic waves are interfered by temperature, wind and various obstacles obstructing the propagation while propagating in air, ultrasonic pulse debounce technique and Kalman filter were applied to TOF and position calculation, respectively, to compensate for the interference and to obtain more accurate moving object position. To perform tasks in real time, ultrasonic signals are processed full-digitally with a Zynq SoC, and as a software design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams. And, a hardware/software co-design is implemented, where the digital circuit portion is designed in the Zynq's fpga and the software portion is c-coded in the Zynq's processors by using the baremetal multiprocessing scheme in which the c-codes are distributed to dual-core processors, cpu0 and cpu1. To verify the usefulness of the proposed system, experiments were performed and the results were analyzed, and it was confirmed that the moving object could be tracked with accuracy of sub-cm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.129-134
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• 2020

Moisture infiltration inside the solar cell module, filling of EVA sheet, melting of the frame seal, and deterioration of power generation performance in the module one year after installation are occurring. Whitening phenomenon, electrode corrosion phenomenon, and dielectric breakdown phenomenon are appearing in solar cell module installed in Korea before 5-7 years, leading to deterioration of power generation performance, and big problems for long-term reliability and long life technology are emerging. Therefore, in order to solve these problems, the development of a micro inverter (MiCrco Inverter Converter, MiC) including the function of securing the durability of the solar cell module and monitoring the aging progress and the solar cell based on the monitoring data from the MiC smart monitoring programs have been proposed to determine the aging of modules. In addition, in order to become a highly efficient solar smart monitoring system through systematic operation management through IT convergence with MiC that has enhanced monitoring function of solar cell module, SoC(System On Chip) in micro inverter is the environment for solar cell module. There is a demand for functions that can detect information in a complex manner and perform communication and control when necessary. Based on these requirements, this paper aims to develop SoC-based low-cost MiC smart photovoltaic system technology.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.792-802
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• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.6
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• pp.515-520
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• 2004

Core-based system-on-a-chip (SoC) designs present a number of test challenges. Two major problems that are becoming increasingly important are long application time during manufacturing test and high volume of test data. Highly efficient compression techniques have been proposed to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. This paper proposes a new test data compression technique for SoC testing. In the proposed technique, compression is achieved by partitioning the test vector set and removing repeating segment. This process has $O(n^{-2})$ time complexity for compression with a simple hardware decoding circuitry. It is shown that the efficiency of the proposed compression technique is comparable with sophisticated software compression techniques with the advantage of easy and fast decoding.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.7-10
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• 2010

In this paper, we design a modem SoC (System on Chip) for low power consumption and high speed wireless communications. Among various schemes of high speed communications, an MB-OFDM (Multi Band-Orthogonal Frequency Division Multiplexing) UWB (Ultra-Wide-Band) chip is designed. The MB-OFDM uses wide-band frequency to provide high speed data rate. Additionally, the system imposes no interference to other services. The 90nm CMOS (Complementary Metal-Oxide Semiconductor) technology is used for the SoC design. Especially, power management mode is implemented to reduce the power consumption.