• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.1
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• pp.17-24
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• 2018

Military camera equipment has a problem that observability is inferior due to various shaking factors. In this paper, we propose an image stabilization algorithm considering performance and execution time to solve this problem and implemented it in Zynq SoC. We stabilized both the simple shaking in the fixed observation position and the sudden shaking in the moving observation position. The feature of the input image is extracted by the Sobel edge algorithm, the subblock with the large edge data is selected, and the motion vector, which is the compensation reference, is calculated through template matching using the 3-step search algorithm of the region of interest. In addition, the proposed algorithm can distinguish the shaking caused by the simple shaking and the movement by using the Kalman filter, and the stabilized image can be obtained by minimizing the loss of image information. To demonstrate the effectiveness of the proposed algorithm, experiments on various images were performed. In comparison, PSNR is improved in the range of 2.6725~3.1629 (dB) and image loss is reduced from 41% to 15%. On the other hand, we implemented the hardware-software integrated design using HLS of Xilinx SDSoC tool and confirmed that it operates at 32 fps on the Zynq board, and realized SoC that operates with real-time processing.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.5
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• pp.133-138
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• 2022

Recently, as GPU performance has improved in HPC and artificial intelligence, its use is becoming more common, but GPU programming is still a big obstacle in terms of productivity. In particular, due to the difficulty of managing host memory and GPU memory separately, research is being actively conducted in terms of convenience and performance, and various CPU-GPU memory transfer programming methods are suggested. Meanwhile, recently many SoC (System on a Chip) products such as Apple M1 and NVIDIA Tegra that bundle CPU, GPU, and integrated memory into one large silicon package are emerging. In this study, data between CPU and GPU devices are used in such an integrated memory device and performance-related research is conducted during transmission. It shows different characteristics from the existing environment in which the host memory and GPU memory in the CPU are separated. Here, we want to compare performance by CPU-GPU data transmission method in NVIDIA SoC chips, which are integrated memory devices, and NVIDIA SMX-based V100 GPU devices. For the experimental workload for performance comparison, a two-dimensional matrix transposition example frequently used in HPC applications was used. We analyzed the following performance factors: the difference in GPU kernel performance according to the CPU-GPU memory transfer method for each GPU device, the transfer performance difference between page-locked memory and pageable memory, overall performance comparison, and performance comparison by workload size. Through this experiment, it was confirmed that the NVIDIA Xavier can maximize the benefits of integrated memory in the SoC chip by supporting I/O cache consistency.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.213-219
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• 2010

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, MC-CDMA, CDMA and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System one Chip) technology, thus a noble modem design proper for SoC technology is necessary. For high speed data transmission of 4G mobile communication services, OFDM scheme has to be applied. But, an OFDM signal consists of a number of independently modulated subcarriers, and superposition of these subcarriers cause a problem that can give a large PAPR. In this paper, a noble modem design for 4G mobile communication services and PAPR reduction method for solving the PAPR problem are proposed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.31-39
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• 2007

In this paper, a system for real-time or periodic measurement and analysis of RF parameters such as forward transmit power and pilot power in CDMA base station systems is proposed. Such RF characteristic parameter measurement can be prevented from system fault and used to achieve optimal service quality and maximum investment return through cell coverage expansion, subscriber capacity increase and so on. For forward power measurement, the local oscillator frequency for the detector is varied so that the transmit power for all channels can be measured. The channel power measurement can be used to analyze the variation in transmit power for changes in voice traffic. By comparing to forward $E_c/I_o$, the pilot channel power can be deducted, which can be used to determine uy degradation in transmit section modules such as the high dover amplifier. Since an accurate analysis of carefully measured data using the CDMA level detector must be made, the system is designed so that measurement errors due to changes in crest factor with modulation method can be overcome.

• The KIPS Transactions:PartC
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• v.18C no.4
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• pp.227-236
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• 2011

IPTV(Internet Protocol Television) is one of the typical businesses which are the convergence of Broadcast and Communication. It provides broadcasting service using IP networks. Recently, IPTV service is developed to Mobile IPTV or Open IPTV. Especially, Open IPTV uses open platform so not only service providers but also general users can provide contents to other users. Open IPTV system has many content providers, so existing security solution of IPTV cannot be adopted. In this paper, we suggest user authentication and key distribution mechanism on Open IPTV. Our proposed mechanism is based on Kerberos, so it can support distribution environment such as Open IPTV. We demonstrate that proposed mechanism can guarantee secure transmission of contents and reduce the delay of user authentication on Open IPTV system compared to other authentication mechanisms. We also compare our proposal and other mechanisms in various aspects, and analyze efficiency and safety of proposed mechanism. As a result, we insist that this mechanism satisfies the security requirements for IPTV.