• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.854-857
• /
• 2015

As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1332-1339
• /
• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.8
• /
• pp.80-88
• /
• 2007

High adaptability and scalability are two critical issues in implementing a very complex system in a single chip. To obtain high adaptability and scalability, novel system design methodology known as communication-based system design has gained large attention from SoC designers. NoC (Network-on-Chip) is such an on-chip communication-based design approach for the next generation SoC design. To provide high adaptability and scalability, NoCs employ network interfaces and routers as their main communication structures and transmit and receive packetized data over such structures. However, data packetization, and routing overhead in terms of run time and area may cost too much compared with conventional SoC communication structure. Therefore, in this research, we propose a novel methodology which automatically generates a hybrid communication structure. In this work, we map traditional pin-to-pin wiring structure for frequent and timing critical communication, and map flexible and scalable structure for infrequent, or highly variable communication patterns. Even though, we simplify the communication structure significantly through our algorithm the connectivity or the scalability of the communication modules are almost maintained as the original NoC design. Using this method, we could improve the timing performance by 49.19%, and the area taken by the communication structure has been reduced by 24.03%.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.773-776
• /
• 1999

For providing good quality power steadily, it is required that operators manipulate the control system of power plant with the good knowledge of power plant system and the control strategies, and cope with accidents effectively. With those requirements, it is general to train operators in power plant control room using full-scope simulator. A full scope simulator adopts the I&C instruments in the main cotrol room, so has to include I/O interface system to interface the simulation computer with I&C instruments in main control room. In already developed simulators, most of I/O interface systems are closed. vendor-dependent. proprietary systems. so have the many disadvantages in terms of cost and maintenance. In this paper. we suggest the method to configure I/O interface system for Thermal Power Plant Simulator based on standard technology which gives the advantages of ease-of-use. cost effectiveness, and simplicity of maintenanceuse by using off-the-shelf products for system integration.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.8A
• /
• pp.820-829
• /
• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of the Korean Ceramic Society
• /
• v.23 no.3
• /
• pp.27-34
• /
• 1986

The hydration of flyash-$Ca(OH)_2-CaSO_4$.$2H_2O$ system was stuedied with varing mixing ratio of flyahs $Ca(OH)_2$ and caSO4.2H2O The samples were steam-cured for 1-7 days at 9$0^{\circ}C$. The optimum mixing composition was flyash : Ca (OH)2=65:35 with 15% $CaSO_4$.42H_2O$ added which produced the hardened material having the best compressive strength (300kg/$cm^2$) Also the low specific gravity(1, 2) of the hardened paste suggests the possibility that it can be used as a light-weight building material. The added $CaSO_4$.42H_2O$ constituted calcium-sulfo-aluminate hydrates which activates the formation of C-S-H hy-drates. Both hydrates developed the strength of hardened paste. The amount of calcium-sulfo-aluminate hydrates was increased when the $CaSO_4$.42H_2O$ was added over 15% however the increased amount did not help the development of strength because of the individually grown calcium-sulfo-aluminate hydrates.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.1
• /
• pp.97-106
• /
• 1997

Software reuse techniques make reapplication of various well-organized information knowledge to system development so that improve productivity and make it easy to maintain software. This paper describes the design and implementation of CSORUS(C and C++ SOurce ReUse System) which can extract reuse components using reverse engineering, and store, retrieve, merge them written with C of C++ programming language. The construction components using reverse engineering has advantage in quality assurance because they are reliable components already tested in real environments.

• ETRI Journal
• /
• v.42 no.4
• /
• pp.518-526
• /
• 2020

This paper presents an efficient hardware random-number generator based on a beta source. The proposed generator counts the values of "0" and "1" and provides a method to distinguish between pseudo-random and true random numbers by comparing them using simple cumulative operations. The random-number generator produces labeled data indicating whether the count value is a pseudo- or true random number according to its bit value based on the generated labeling data. The proposed method is verified using a system based on Verilog RTL coding and LabVIEW for hardware implementation. The generated random numbers were tested according to the NIST SP 800-22 and SP 800-90B standards, and they satisfied the test items specified in the standard. Furthermore, the hardware is efficient and can be used for security, artificial intelligence, and Internet of Things applications in real time.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2006.06a
• /
• pp.81-84
• /
• 2006

본 논문에서는 시스템 수준 설계 언어인 SystemC를 이용하여 디지털 이미지 프로세싱의 한 부분인 Edge Detector 구현에 대하여 기술한다. Edge Detector는 마스크의 가운데 픽셀을 강조하는 Sobel 알고리즘을 사용하여 모델링 하였으며, 설계된 디자인의 동작은 간단한 BMP 파일을 적용하여 검증하였다. 또한 Edge Detector를 구성하는 하위 모듈들 간의 연결을 각각 sc_buffer 채널과 so_fifo 채널을 이용하여 설계하였을 때의 실행시간을 비교하였다.

• THE INTERNATIONAL COMMERCE & LAW REVIEW
• /
• v.59
• /
• pp.137-157
• /
• 2013

The Electronic Trade Finance not only has with the trait which is simple procedures, low cost but also easier access to using statistics compare to formerly paper based system. In Korea, all of trade finance system will be changed to electronic base by February 2014. The purpose of this research finds the using status and problems of the electronic local L/C and electronic purchase certificate, and suggests several improvements. First, the whole trade finance system should improve in terms of simple procedures, especially small and medium companies can use the system sufficient maximum limit. Second, the organizers, KTNET, KITA etc, need to the new electronic trade finance system promote to customers and training program for early settlement. It also has to manage at an unified system between IT and tex authorities. Third, small and medium size companies still think the charge for using high, so it need to make a resonable charge for using the electronic system to persuasive extent reasonable about it.