• Journal of IKEEE
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• v.16 no.4
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• pp.375-381
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• 2012

In this paper, we present an implementation of Viola-Jones algorithm in a multi-core SoC by using skin color information and a parallel processing method. In order to reduce unnecessary operations and improve the detection speed, we adopted a face detection algorithm based on skin color and deleted background image. The algorithm is functionally divided into several parts taking account of the size and the dependency so that the divided functions can be proceeded in parallel. Experiment results in SoC with built-in Cortex-A9 multi core show that it is about 1.8 times faster than the existing algorithm which is not divided.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10b
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• pp.928-933
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• 1988

Control technology has been making remarkable progress in electrical control (E), instrumentation & control (I) and computer control (C) field respectively. In order to rationalize system engineering and simplify system configuration and operation work, so called, EIC are now to be integrated into one system. FUJI has developed it's own E, I&C integrated system, to meet above mentioned market requirements of variety. This paper describes basic concept of FUJI's Integrated Man-Machine Interface, hereinafter called SINGLE CONSOLE, from some view points of E, I, C integration technology.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.359-360
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• 2010

In smart grid system which uses photovoltaic system, fuel cells and so on, a program implemented with C language is used for control and measurement. When using programs implemented with C language GUI is difficult to watch control and monitor the smart grid system. But LabVIEW is a graphical programming language and it is easy to design GUI screen and to manage many variables such as real-time output of electric power including solar cell, wind power system and fuel cell. This paper suggests LabVIEW and C-language TCP/IP communication for smart grid monitoring system i mplemented with C-language.

• Electronics and Telecommunications Trends
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• v.28 no.2
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• pp.58-69
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• 2013

LTE 기반의 펨토셀 활용과 개발에 대한 요구는 LTE로의 이동통신 서비스가 본격화되면서, 최근 몇 년간 중요한 이슈로 자리매김하고 있다. 기지국 장비의 재설치와 주파수의 효율적인 활용 측면에서 펨토셀 기지국은 이동통신 서비스 사업자와 가입자에게 동시에 중요한 역할을 수행할 것으로 보인다. 이러한 펨토셀 기지국의 필요성을 충족시켜 주기 위해서는 펨토셀 기지국의 형상과 기능에서 그 본래의 요구를 만족시켜 주는 것이 중요하다. 무엇보다도, LTE 기반의 펨토셀 기지국은 기기의 간편한 설치와 매크로셀 기지국의 오프로딩이라는 역할을 충실히 수행할 수 있는지가 핵심적 평가 요소가 될 것이다. 이를 위해서는 펨토셀 기지국의 핵심 부품인 베이스밴드 SoC(System on a Chip) 성능 및 기능이 펨토셀 기지국 전체의 경쟁력을 판단하는 데 중요한 척도 중에 하나가 될 것이다. 본고에서는 이러한 관점에서 ETRI가 개발한 LTE 펨토셀 기지국의 베이스밴드 SoC를 중심으로 그 형상과 개발 과정을 기술하고 해외 업체들의 베이스밴드 칩셋의 형상과 개발상황에 대해서 자세히 기술하기로 한다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.3
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• pp.156-162
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• 2003

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.100-102
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• 2003

멀티미디어 데이터 처리나 암호화 알고리즘과 같은 계산양이 많고 빠른 시간 안에 처리되어야하는 어플리케이션들을 처리하기 위하여 재구성 가능한 논리소자와 내장형 마이크로 프로세서등이 하나의 칩에 통합된 재구성 가능한 SoC가 폭넓게 활용되고 있다. 이러한 컴퓨팅 환경의 시장적응성을 높이기위해서는 프로토타입을 제작하기 전에 설계변수에 따른 성능수치를 이미 예측하여 최소의 비용으로 시스템의 수행 시간 및 자원제약사향을 만족할 수 있는 구조를 찾아내는 것이 필수적이다. 본 논문에서는 Y-chart 설계 방법의 기본 개념을 재구성 가능한 SoC에 적용가능하도록 확장하여, 시스템 수준의 설계공간 탐색 도구를 개발하였다. 구현된 설계 공간 탐색을 통한 시뮬레이션 결과는 시스템 설계자들에게 실제 포로토타입을 구축하지 않고 최적의 설계변수를 결정할 수 있게 하여 설계시간과 설계비용을 현저하게 줄여줄 것으로 기대된다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.961-962
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• 2006

The AMBA(Advanced Microcontroller Bus Architecture) system is one of the most important elements having an influence upon system performance in ARM-based SoC environments. The system guarantees easy connection and good performance as a 32-bit bus system for ARM processors. In this paper, we analyze arbitration algorithms for the AHB bus of the AMBA system and propose an efficient algorithm to improve the performance of the bus system.

• Nuclear Engineering and Technology
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• v.45 no.5
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• pp.653-664
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• 2013

The design of computer-based instrumentation and control (I&C) systems is determined by the allocation of I&C functions to I&C systems and components. Due to the characteristics of computer-based technology, component failures can negatively affect several I&C functions, so that the reliability proof of the I&C systems requires the accomplishment of I&C system design analyses throughout the I&C life-cycle. On one hand, this paper proposes the restructuring of the sequential IEC 61513 I&C life-cycle according to the V-model, so as to adequately integrate the concept of verification and validation. On the other hand, based on a metamodel for the modeling of I&C systems, this paper introduces a method for the modeling and analysis of the effects with respect to the superposition of failure combinations and event sequences on the I&C system design, i.e. the temporal change of physical structure is analyzed. In the first step, the method is concerned with the modeling of the I&C systems. In the second step, the method considers the analysis of temporal change of physical structure, which integrates the concepts of the diversity and defense-in-depth analysis, fault tree analysis, event tree analysis, and failure mode and effects analysis.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.553-556
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• 2004

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

• Journal of Korean Ophthalmic Optics Society
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• v.6 no.2
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• pp.71-75
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• 2001

In this paper, a three-dimensional measuring system of thermoluminescence(TL) spectra based on temperature, wavelength and luminescence intensity was introduced. The system was composed of a spectrometer, temperature control unit for thermal stimulation, photon detector and personal computer for control the entire system. Temperature control was achieved by using feedback to ensure a linear-rise in the sample temperature. Digital multimeter(KEITHLEY 195A) measures the electromotive force of Copper-Constantan thermocouple and then transmits the data to the computer through GPIB card. The computer converts this signal to temperature using electromotive force-temperature table in program, and then control the power supply through the D/A converter. The spectrometer(SPEX 1681) is controlled by CD-2A, which is controlled by the computer through RS-232 communication port. For measuring the luminescence intensity during the heating run, the electrometer(KEITHLEY 617) measures the anode current of photomultiplier tube(HAMAMATSU R928) and transmits the data to computer through the A/D converter. And, we measured and analyzed thermoluminescence of $CaSO_4$ : Dy, P using the system. The measuring range of thermoluminescence spectra was 300K-575K and 300~800 nm, $CaSO_4$ : Dy. P was fabricated by the Yamashita's method in Korea Atomic Energy Research Institute(KAERI) for radiation dosimeter. Thermoluminesce spectra of the $CaSO_4$ : Dy, P consist of two main peak at temperature of $205^{\circ}C$, wavelength 476 nm and 572 nm and with minor ones at 658 nm and 749 nm.