• Title/Summary/Keyword: SoC 테스트

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A Grammar Development Environment for Feature-based APSG (자질 기반 구 구조 문법을 위한 문법 개발 환경)

  • 심광섭;양재형
    • Journal of KIISE:Software and Applications
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    • v.31 no.10
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    • pp.1418-1429
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    • 2004
  • This paper presents GrammE, a grammar development environment for feature-based APSG. At the stage of a grammar development, analysis are be done by interpreting the grammar under development, given in a text format, it is relatively easy to diagnose the grammar. Once developed, the grammar is compiled, by using the embedded grammar compiler, into a parser program written in $C^{++}$. The parser program can be used in various types of natural language processing systems requiring syntactic analysis. GrammE is language-independent, and so far has been used for the development of Korean and Chinese grammars.

XML Digital signature System based on Mobile Environment (모바일 환경에서의 XML 문서 디지털 서명 시스템)

  • Hao, Ri-Ming;Hong, Xian-Yu;Lee, Seong-Hyun;Lee, Jae-Seung;Jung, Hoe-Kyung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.701-704
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    • 2007
  • Recently, More and more consumer enjoy the finance service such as settling, account transferring, stocks investment, and so via mobile device. In the mobile environment, data transferring between the devices is formatted as XML. However, the common XML file is exposed to the attack such as hacking and malignity code, to satisfy security of mobile environment is very difficult. The problem is more seriously at the open platform such as WIPI that is developed by our country. So there is enough reason to propose one system to protect the import data. In this paper, we development the system to digital signature and signature the XML document in order to protect data, and the system is observing the recommendation of the XML Signature Syntax and Processing by W3C. When designing and composition the system, we use the digital signature algorithm RSA, DSA, KCDSA, and HMAC, etc. we test the system at the open WIPI platform.

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Vulnerability analysis on the ARMv7 Thumb Architecture (ARMv7 Thumb Architecture 취약성 분석)

  • Kim, Si-Wan;Seong, Ki-Taek
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.5
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    • pp.1003-1008
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    • 2017
  • The Internet of Things has attracted considerable research attention in recent years. In order for the new IoT technology to be widely used, the reliability and protection of information is required. IoT systems are very vulnerable to physical security due to their easy accessibility. Along with the development of SoC technology, many operating systems have been developed and many new operating systems have been introduced. In this paper, we describe the vulnerability analysis results for operating systems running on the ARMv7 Thumb Architecture hardware platform. For the recently introduced "Windows 10 IoT Core" operating system, I implemented the Zero-Day Attack by implanting the penetration code developed through the research into a specific IoT system. The virus detection test for the resulting penetration code was validated by referral to the "virustotal" site.

A Design of AES-based CCMP core for IEEE 802.11i Wireless LAN Security (IEEE 802.11i 무선 랜 보안을 위한 AES 기반 CCMP 코어 설계)

  • Hwang Seok-Ki;Kim Jong-Whan;Shin Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.6A
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    • pp.640-647
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    • 2006
  • This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

Classification and analysis of error types for deep learning-based Korean spelling correction (딥러닝 기반 한국어 맞춤법 교정을 위한 오류 유형 분류 및 분석)

  • Koo, Seonmin;Park, Chanjun;So, Aram;Lim, Heuiseok
    • Journal of the Korea Convergence Society
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    • v.12 no.12
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    • pp.65-74
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    • 2021
  • Recently, studies on Korean spelling correction have been actively conducted based on machine translation and automatic noise generation. These methods generate noise and use as train and data set. This has limitation in that it is difficult to accurately measure performance because it is unlikely that noise other than the noise used for learning is included in the test set In addition, there is no practical error type standard, so the type of error used in each study is different, making qualitative analysis difficult. This paper proposes new 'error type classification' for deep learning-based Korean spelling correction research, and error analysis perform on existing commercialized Korean spelling correctors (System A, B, C). As a result of analysis, it was found the three correction systems did not perform well in correcting other error types presented in this paper other than spacing, and hardly recognized errors in word order or tense.

Compact CNN Accelerator Chip Design with Optimized MAC And Pooling Layers (MAC과 Pooling Layer을 최적화시킨 소형 CNN 가속기 칩)

  • Son, Hyun-Wook;Lee, Dong-Yeong;Kim, HyungWon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.9
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    • pp.1158-1165
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    • 2021
  • This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm2. The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

Synthesis and Electrochemical Characteristics of Carbon added Li3V2(PO4)3 (탄소첨가한 Li3V2(PO4)3의 합성 및 전기화학적 특성)

  • Jo, Yeong-Im;Na, Byung-Ki
    • Journal of the Korean Electrochemical Society
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    • v.15 no.2
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    • pp.101-108
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    • 2012
  • The purpose of this study was to improve the conductivity of $Li_3V_2(PO_4){_3}$ by adding carbon source so that the discharge rate and cyclic properties were improved. Glucose and CNT were added to $Li_3V_2(PO_4){_3}$ and the structure and electrochemical properties were studied. $Li_3V_2(PO_4){_3}$, $Li_3V_2(PO_4){_3}$/C and $Li_3V_2(PO_4){_3}$/CNT were synthesised by solid state reaction using hydrogen reduction method at 600, 700, 800, $900^{\circ}C$. The cathode materials were assembled to coin cell type 2032 with Lithium metal as a counter electrode. The coin cell was galvanostatically evaluated in the voltage range of 3.0~4.8 V.

MLC NAND-type Flash Memory Built-In Self Test for research (MLC NAND-형 Flash Memory 내장 자체 테스트에 대한 연구)

  • Kim, Jin-Wan;Kim, Tae-Hwan;Chang, Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.3
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    • pp.61-71
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    • 2014
  • As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

Feature Extraction based FE-SONN for Signature Verification (서명 검증을 위한 특정 기반의 FE-SONN)

  • Koo Gun-Seo
    • Journal of the Korea Society of Computer and Information
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    • v.10 no.6 s.38
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    • pp.93-102
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    • 2005
  • This paper proposes an approach to verify signature using autonomous self-organized Neural Network Model , fused with fuzzy membership equation of fuzzy c-means algorithm, based on the features of the signature. To overcome limitations of the functional approach and Parametric approach among the conventional on-line signature recognition approaches, this Paper presents novel autonomous signature classification approach based on clustering features. Thirty-six globa1 features and twelve local features were defined, so that a signature verifying system with FE-SONN that learns them was implemented. It was experimented for total 713 signatures that are composed of 155 original signatures and 180 forged signatures yet 378 original signatures written by oneself. The success rate of this test is more than 97.67$\%$ But, a few forged signatures that could not be detected by human eyes could not be done by the system either.

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A Design and Implementation of a Home Gateway based on the RTC Technology Supporting Live Video Streaming (라이브 비디오 스트리밍을 지원하는 RTC 기반 홈 게이트웨이의 설계 및 구현)

  • Kim, Hye-Sun;Hwang, Ki-Tae
    • The KIPS Transactions:PartC
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    • v.12C no.4 s.100
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    • pp.589-596
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    • 2005
  • The objective of this paper lies in the design and implementation of a home gateway supporting live video streaming which flows from the Non-SIP video camera in home to the mobile SIP device outside. We developed the home gateway on the OSGi framework and employed the RTC technology which embeds an SIP stack so that the multimedia session can be established from the home device to the mobile user outside. And also we developed an RTC bundle to manage the session and a virtual capture device driver to read the video stream from the Non-SIP video camera in the home network, and installed them on the home gateway. Finally, we constructed the experimental environment that has the windows messenger as the SIP mobile device and an AXIS 2100 UPnP video camera as a video source, and then tested if the session establishment to the mobile user from the camera and live video streaming work well between them.