• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1948-1956
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• 2000

본 논문은 보드 레벨 테스팅 및 경계주사기법의 응용을 위한 테스트 버스 콘트롤러의 설계와 구현에 관해 다룬다. 테스트 버스 콘트롤러는 프로세서와 인터페이스를 통하여 IEEE 1149.1 테스트 버스를 제어하기 위한 칩이다. 최근 들어 IEEE 1149.1은 여러 분야에서 응용되어지고 있어서 다양한 응용분야에 적합한 테스트 버스 콘트롤러의 설계가 요구된다. 보드 레벨 테스팅을 위해서 SVF에 정의된 테스트를 수행할 수 있어야 하며, System-on-a-Chip (SoC) 설계 방식에서 내장되어지기 위해서는 작은 칩 크기와 높은 고장 검출률을 가져야 한다. 본 논문에서 구현된 칩은 기존의 테스트 장비에서 널리 쓰이는 SVF에 정의된 테스트를 모두 지원하며, 12k 게이트 정도의 크기를 가진다. 또한 독립적인 칩으로 쓰일 경우는 테스트 버스 콘트롤러가 버스 슬래이브로 쓰일 수 있으므로 IEEE 1149.1 테스트 회로를 가지도록 설계하였다.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.37-44
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• 2005

This paper presents effective test patterns and their BIST implementations for SoC and Board interconnects. Initially '6n'algorithm, where 'n' is the total number of interconnect nets, is introduced to completely detect and diagnose both static and crosstalk faults. Then, more economic 4n+1 algorithm is described to perfectly capture the crosstalk faults for the interconnect nets separated within a certain distance. It will be shown that both algorithms can be easily implemented as interconnect BIST hardwares with small area penalty than conventional LFSR.

• Journal of IKEEE
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• v.18 no.4
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• pp.495-501
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• 2014

In this paper, we designed a diversity modem hardware architecture for IEEE802.11p WAVE and tested the modem on the road with car attached shark antenna. One of the dual channel modem and the diversity single modem with maximum ratio combining algorithm can be selected on the designed architecture. The designed modem have been implemented on the Xillinx Kintex7 FPGA. We tested the modem performance on the smart highway experience road. As experimental results, we can verify the performance of the diversity modem on real road and the enlarged communication range by more than 30%.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.487-490
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• 2004

상황 인식(context-awrare)은 인간-컴퓨터 상호작용의 단점을 극복하기 위한 방법으로써 많은 주목을 받고 있다. 이 논문에서는 SoC(System-on-a-Chip)로 구현될 수 있는 상황 인식 시스템 구조를 제안한다. 제안한 구조는 센서 추상화, 컨텍스트 변경에 대한 통지 메커니즘, 모듈식 개발, if-then규칙을 이용한 쉬운 서비스 구성과 유연한 상황 인식 서비스 구현을 지원한다. 이 구조는 통신 모듈, 처리 모듈, 블랙보드를 포함하는 SoC 마이크로프로세서 부분과 규칙 기반 시스템 모듈을 구현한 하드웨어로 구성된다. 규칙 기반 시스템 하드웨어는 모든 규칙의 조건부에 대해 매칭 연산을 병렬로 수행하고, 규칙의 결론부는 마이크로프로세서에 내장된 행위 모듈을 호출함으로써 작업을 수행한다. 제안한 구조의 SoC 시스템은 SystemC SoC 개발 환경에서 설계되고, 성공적으로 테스트되었다. 제안한 SoC 기반의 상황 인식 시스템 구조는 주거 환경에서 컨텍스트를 인식하여 노인을 보조하는 지능형 이동 로봇 등에 적용될 수 있을 것으로 기대된다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.114-121
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• 2013

As the weight of embedded memory within Systems-On-Chips(SoC) rapidly increases to 80-90% of the number of total transistors, the importance of testing embedded memory in SoC increases. This paper proposes IEEE std. 1500 wrapper based Programmable Memory Built-In Self-Test(PMBIST) architecture which can support various kinds of test algorithm. The proposed PMBIST guarantees high flexibility, programmability and fault coverage using not only March algorithms but also non-March algorithms such as Walking and Galloping. The PMBIST has an optimal hardware overhead by an optimum program instruction set and a smaller program memory. Furthermore, the proposed fault information processing scheme guarantees improvement of the memory yield by effectively supporting three types of the diagnostic methods for repair and diagnosis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1679-1682
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• 2005

최근 SoC를 포함하는 대부분의 임베디드시스템에서는 RTOS가 선택이 아닌 필수적인 구성요소가 됨에 따라 SoC 개발의 초기단계에서부터 RTOS를 도입하는 것이 바람직하다. 하지만, 기존의 범용 RTOS가 제공하는 기능은 대부분 응용 소프트웨어의 개발과 수행을 위한 것으로 SoC 개발 및 검증에는 적합하지 않은 문제점을 가지고 있다. 본 연구에서는 SoC 개발을 위해 운영체제가 만족시켜야할 요구사항을 제시하고, 소프트웨어의 재사용성과 SoC의 검증을 함께 지원하는 VPOS(Verification-Purpose OS)를 개발하였다. VPOS는 초경량의 단순한 계층적 구조(layered structure)를 가지는 RTOS로서 소프트웨어 재사용을 위해 POSIX 표준 API, 유닉스 호환 디바이스 드라이버 인터페이스, HAL 등을 제공한다. 또한 SoC 설계의 검증을 위해 RT 수준의 통합시뮬레이션에 적합한 커널 구조 및 최적화된 코드, 하드웨어 테스트를 위한 쉘 명령어, 응용 소프트웨어의 디버깅을 위한 KREM(kernel resource and event monitoring) 등의 특징을 함께 제공한다.