• Title/Summary/Keyword: Smart-chip

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Analysis of a Buck DC-DC Converter for Smart Electronic Applications (스마트기기용 강압형 DC-DC 변환기 특성해석)

  • Kang, Bo-gyeong;Na, Jae-Hun;Song, Han-Jung
    • Journal of the Korean Society of Industry Convergence
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    • v.22 no.3
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    • pp.373-379
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    • 2019
  • Nowadays, the IoT portable electronic devices have become more useful and diverse, so they require various supply voltage levels to operate. This paper presents a DC-DC buck converter with pulse width modulation (PWM) for portable electronic devices. The proposed step-down DC-DC converter consists of passive elements such as capacitors, inductors, and resistors and an integrated chip (IC) for signal control to reduce power consumption and improves ripple voltage with the resolution. The proposed DC-DC converter is simulated and analyzed in PSPICE circuit design platform, and implemented on the prototype PCB board with a Texas Instruments LM5165 IC. The proposed buck converter is showed 92.6% of peak efficiency including a load current range of 4-10 mA, 3.29 mV of the voltage ripple at 5 V output voltage for the supply voltage 12 V. Measured and Simulated power efficiency are made good agreement with each other.

New Thyristor Based ESD Protection Devices with High Holding Voltages for On-Chip ESD Protection Circuits

  • Hwang, Suen-Ki;Cheong, Ha-Young
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.2
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    • pp.150-154
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    • 2019
  • In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

Wearable Computers

  • Cho, Gil-Soo;Barfield, Woodrow;Baird, Kevin
    • Fiber Technology and Industry
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    • v.2 no.4
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    • pp.490-508
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    • 1998
  • One of the latest fields of research in the area of output devices is tactual display devices [13,31]. These tactual or haptic devices allow the user to receive haptic feedback output from a variety of sources. This allows the user to actually feel virtual objects and manipulate them by touch. This is an emerging technology and will be instrumental in enhancing the realism of wearable augmented environments for certain applications. Tactual displays have previously been used for scientific visualization in virtual environments by chemists and engineers to improve perception and understanding of force fields and of world models populated with the impenetrable. In addition to tactual displays, the use of wearable audio displays that allow sound to be spatialized are being developed. With wearable computers, designers will soon be able to pair spatialized sound to virtual representations of objects when appropriate to make the wearable computer experience even more realistic to the user. Furthermore, as the number and complexity of wearable computing applications continues to grow, there will be increasing needs for systems that are faster, lighter, and have higher resolution displays. Better networking technology will also need to be developed to allow all users of wearable computers to have high bandwidth connections for real time information gathering and collaboration. In addition to the technology advances that make users need to wear computers in everyday life, there is also the desire to have users want to wear their computers. In order to do this, wearable computing needs to be unobtrusive and socially acceptable. By making wearables smaller and lighter, or actually embedding them in clothing, users can conceal them easily and wear them comfortably. The military is currently working on the development of the Personal Information Carrier (PIC) or digital dog tag. The PIC is a small electronic storage device containing medical information about the wearer. While old military dog tags contained only 5 lines of information, the digital tags may contain volumes of multi-media information including medical history, X-rays, and cardiograms. Using hand held devices in the field, medics would be able to call this information up in real time for better treatment. A fully functional transmittable device is still years off, but this technology once developed in the military, could be adapted tp civilian users and provide ant information, medical or otherwise, in a portable, not obstructive, and fashionable way. Another future device that could increase safety and well being of its users is the nose on-a-chip developed by the Oak Ridge National Lab in Tennessee. This tiny digital silicon chip about the size of a dime, is capable of 'smelling' natural gas leaks in stoves, heaters, and other appliances. It can also detect dangerous levels of carbon monoxide. This device can also be configured to notify the fire department when a leak is detected. This nose chip should be commercially available within 2 years, and is inexpensive, requires low power, and is very sensitive. Along with gas detection capabilities, this device may someday also be configured to detect smoke and other harmful gases. By embedding this chip into workers uniforms, name tags, etc., this could be a lifesaving computational accessory. In addition to the future safety technology soon to be available as accessories are devices that are for entertainment and security. The LCI computer group is developing a Smartpen, that electronically verifies a user's signature. With the increase in credit card use and the rise in forgeries, is the need for commercial industries to constantly verify signatures. This Smartpen writes like a normal pen but uses sensors to detect the motion of the pen as the user signs their name to authenticate the signature. This computational accessory should be available in 1999, and would bring increased peace of mind to consumers and vendors alike. In the entertainment domain, Panasonic is creating the first portable hand-held DVD player. This device weight less than 3 pounds and has a screen about 6' across. The color LCD has the same 16:9 aspect ratio of a cinema screen and supports a high resolution of 280,000 pixels and stereo sound. The player can play standard DVD movies and has a hour battery life for mobile use. To summarize, in this paper we presented concepts related to the design and use of wearable computers with extensions to smart spaces. For some time, researchers in telerobotics have used computer graphics to enhance remote scenes. Recent advances in augmented reality displays make it possible to enhance the user's local environment with 'information'. As shown in this paper, there are many application areas for this technology such as medicine, manufacturing, training, and recreation. Wearable computers allow a much closer association of information with the user. By embedding sensors in the wearable to allow it to see what the user sees, hear what the user hears, sense the user's physical state, and analyze what the user is typing, an intelligent agent may be able to analyze what the user is doing and try to predict the resources he will need next or in the near future. Using this information, the agent may download files, reserve communications bandwidth, post reminders, or automatically send updates to colleagues to help facilitate the user's daily interactions. This intelligent wearable computer would be able to act as a personal assistant, who is always around, knows the user's personal preferences and tastes, and tries to streamline interactions with the rest of the world.

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Pattern Testable NAND-type Flash Memory Built-In Self Test (패턴 테스트 가능한 NAND-형 플래시 메모리 내장 자체 테스트)

  • Hwang, Phil-Joo;Kim, Tae-Hwan;Kim, Jin-Wan;Chang, Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.6
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    • pp.122-130
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    • 2013
  • The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

MLC NAND-type Flash Memory Built-In Self Test for research (MLC NAND-형 Flash Memory 내장 자체 테스트에 대한 연구)

  • Kim, Jin-Wan;Kim, Tae-Hwan;Chang, Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.3
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    • pp.61-71
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    • 2014
  • As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

An On-chip ESD Protection Method for Preventing Current Crowding on a Guard-ring Structure (가드링 구조에서 전류 과밀 현상 억제를 위한 온-칩 정전기 보호 방법)

  • Song, Jong-Kyu;Jang, Chang-Soo;Jung, Won-Young;Song, In-Chae;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.105-112
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    • 2009
  • In this paper, we investigated abnormal ESD failure on guard-rings in the smart power IC fabricated with $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology. Initially, ESD failure occurred below 200 V in the Machine Model (MM) test due to current crowding in the parasitic diode associated with the guard-rings which are generally adopted to prevent latch-up in high voltage devices. Optical Beam Induced Resistance Charge (OBIRCH) and Scanning Electronic Microscope (SEM) were used to find the failure spot and 3-D TCAD was used to verify cause of failure. According to the simulation results, excessive current flows at the comer of the guard-ring isolated by Local Oxidation of Silicon (LOCOS) in the ESD event. Eventually, the ESD failure occurs at that comer of the guard-ring. The modified comer design of the guard-ring is proposed to resolve such ESD failure. The test chips designed by the proposed modification passed MM test over 200 V. Analyzing the test chips statistically, ESD immunity was increased over 20 % in MM mode test. In order to avoid such ESD failure, the automatic method to check the weak point in the guard-ring is also proposed by modifying the Design Rule Check (DRC) used in BCD technology. This DRC was used to check other similar products and 24 errors were found. After correcting the errors, the measured ESD level fulfilled the general industry specification such as HBM 2000 V and MM 200V.

Characterization of the Immune Regulation Function of Fibroblastic Reticular Cells Originating from Lymph Node Stroma (림프절 스트로마 유래 fibroblastic reticular cell의 면역조절 기능에 대한 특성 규명)

  • Lee, Jong-Hwan
    • Journal of Life Science
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    • v.26 no.7
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    • pp.789-795
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    • 2016
  • A lymph node (LN) is one of the secondary lymphoid organs. An LN consists of a complicated 3 dimensional frame structure and several stromal cells. Fibroblastic reticular cells (FRC) are distributed in the T zone for interaction with T cells. FRC secrete homing chemokines such as CCL19 and CCL21. Moreover, FRC play a pivotal role in the production of extracellular matrix (ECM) into LN for ECM reorganization against pathogen infections. However, not much is known about the involvement of the immune reaction of FRC. The present report is for the characterization of FRC on immune response. For this, FRC were positioned in several infected situations such as co-culture with macrophage, lipopolysaccharide (LPS), and TNFα stimulation. When a co-culture between FRC and macrophage was performed, a morphological change in FRC was observed, and empty space between FRCs was created by this change. The soluble ICAM-1 protein level was up-regulated by co-culturing with Raw264.7 and the treatment of the ROCK inhibitor Y27632. The activity of matrix metalloproteinase (MMP) was up-regulated by LPS onto FRC. Furthermore, the inflammatory cytokine TNFα regulated the expression of ECM in FRC by a gene chip assay. Collectively, it suggests that FRC are involved in immune reactions.

Design and Analysis of a 12 V PWM Boost DC-DC Converter for Smart Device Applications (스마트기기를 위한 12 V 승압형 PWM DC-DC 변환기 설계 및 특성해석)

  • Na, Jae-Hun;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.239-245
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    • 2016
  • In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

Development of the Precision Image Processing System for CAS-500 (국토관측위성용 정밀영상생성시스템 개발)

  • Park, Hyeongjun;Son, Jong-Hwan;Jung, Hyung-Sup;Kweon, Ki-Eok;Lee, Kye-Dong;Kim, Taejung
    • Korean Journal of Remote Sensing
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    • v.36 no.5_2
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    • pp.881-891
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    • 2020
  • Recently, the Ministry of Land, Infrastructure and Transport and the Ministry of Science and ICT are developing the Land Observation Satellite (CAS-500) to meet increased demand for high-resolution satellite images. Expected image products of CAS-500 includes precision orthoimage, Digital Surface Model (DSM), change detection map, etc. The quality of these products is determined based on the geometric accuracy of satellite images. Therefore, it is important to make precision geometric corrections of CAS-500 images to produce high-quality products. Geometric correction requires the Ground Control Point (GCP), which is usually extracted manually using orthoimages and digital map. This requires a lot of time to acquire GCPs. Therefore, it is necessary to automatically extract GCPs and reduce the time required for GCP extraction and orthoimage generation. To this end, the Precision Image Processing (PIP) System was developed for CAS-500 images to minimize user intervention in GCP extraction. This paper explains the products, processing steps and the function modules and Database of the PIP System. The performance of the System in terms of processing speed, is also presented. It is expected that through the developed System, precise orthoimages can be generated from all CAS-500 images over the Korean peninsula promptly. As future studies, we need to extend the System to handle automated orthoimage generation for overseas regions.

Fibroblastic Reticular Cell Derived from Lymph Node Is Involved in the Assistance of Antigen Process (림프절 유래 fibroblastic reticular cell의 효율적 항원처리 관련성에 대한 연구)

  • Kim, Min Hwan;Lee, Jong-Hwan
    • Journal of Life Science
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    • v.26 no.9
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    • pp.1027-1032
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    • 2016
  • Antigen is substance causing disease derived from pathogen. Living organism has the immune system in terms of defense mechanism against antigen. Antigen is processed through several pathways such as phagocytosis, antibody action, complement activation, and cytotoxins by NK or cytotoxic T lymphocyte via MHC molecule. Lymph node (LN) is comprised of the complicated 3 dimensional network and several stromal cells. Fibroblastic reticular cells (FRC) are distributed in T zone for interaction with T cells. FRC produces the extra cellular matrix (ECM) into LN for ECM reorganization against pathogen infections and secretes homing chemokines. However, it has not so much been known about the involvement of the antigen process of FRC. The present report is for the function of FRC on antigen process. For this, FRC was positioned with several infected situations such as co-culture with macrophage, T cell, lipopolysaccharide (LPS) and TNFα stimulation. When co-culture between FRC with macrophage and T cells was performed, morphological change of FRC was observed and empty space between FRCs was made by morphological change. The matrix metallo-proteinase (MMP) activity was up-regulated by Y27632 and T cells onto FRC. Furthermore, inflammatory cytokine, TNFα regulated the expression of adhesion molecules and MHC I antigen transporter in FRC by gene chip assay. NO production was elevated by FRC monolayer co-cultured with macrophage stimulated by LPS. GFP antigen was up-taken by macrophage co-cultured with FRC. Collectively, it suggests that FRC assists of the facilitation of antigen process and LN stroma is implicated into antigen process pathway.