• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• 조명전기설비학회논문지
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• 제29권1호
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• pp.1-8
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• 2015

To produce the white light, there are a single chip method using the blue light and phosphor coating, a multi chip method by mixing R, G, B light.. Multi chip method is proper for the smart lighting system by controling color and color temperature. And color rendering of single chip LED is good by even spectral distribution. To apply application technic like smart light system, this paper analyzed the properties of single chip LED and RGB multi chip LED, and implemented the 2 part subject evaluation for single chip LED and RGB multi chip LED. The first part is comparison of properties for single chip LED and RGB multi chip and second part is color appearance evaluation of 8 colors in each lighting environment.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.71-76
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• 2012

SnBi 저온솔더의 플립칩 공정을 이용한 스마트 의류용 칩 접속공정에 대해 연구하였다. 캐리어 필름에 형성한 Cu 리드프레임을 $130^{\circ}C$에서 직물에 열압착 시킴으로써 Cu 리드프레임이 전사된 직물 기판을 형성하였다. 칩 시편에 SnBi 페이스트를 도포하여 솔더범프를 형성한 후 직물 기판의 Cu 리드프레임에 배열하고 $180^{\circ}C$에서 60초 동안 유지시켜 플립칩 본딩하였다. SnBi 저온솔더를 사용하여 형성된 스마트 의류용 플립칩 접속부의 평균 접속저항은 $9m{\Omega}$이었다.

• 스마트미디어저널
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• 제1권1호
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• pp.27-35
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• 2012

본 논문은 온칩 네트워크 기반 플랫폼을 이용한 멀티미디어 비디오 코덱의 성능 분석에 대해 기술한다. 최근에 멀티미디어 SoC 통신 구조로 등장한 온칩 네트워크(On-Chip Network)는 기존의 SoC 설계에 사용된 온칩 버스(On-Chip Bus) 구조의 문제점을 해결하는 통신 구조로서 데이터 통신의 병렬성 제공으로 인한 고성능, 재사용성, 확장성을 제공하는 통신 구조이다. 온칩 네트워크 기반 MPEG-4, H.264의 성능과 온칩 버스와 성능을 비교 분석하였다. 실험 결과, 온칩 네트워크 기반 MPEG-4, H.264의 성능이 온칩 버스에 비해 33~56%의 성능이 개선되었다.

• 센서학회지
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• 제20권3호
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• pp.162-167
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• 2011

In this paper, we propose a vision system using a field programmable gate array(FPGA) and a smart vision chip. The output of the vision chip is varied by illumination conditions. This chip is suitable as a surveillance system in a dynamic environment. However, because the output swing of a smart vision chip is too small to definitely confirm the warning signal with the FPGA, a modification was needed for a reliable signal. The proposed system is based on a transmission control protocol/internet protocol(TCP/IP) that enables monitoring from a remote place. The warning signal indicates that some objects are too near.

• ETRI Journal
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• 제26권1호
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• pp.1-6
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• 2004

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and ${\sqrt{T}}$-dependent thermal red shifts. We observed uniform bottom emissions from a 1-kb smart pixel chip of a $32{\times}32$ InGaAs PQR laser array flip-chip bonded to a 0.35 ${\mu}m$ CMOS-based PQR laser driver. The PQR-CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.89-110
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• 2005

A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

• Journal of the Korean Data and Information Science Society
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• 제20권1호
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• pp.125-137
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• 2009

스마트카드는 작은 크기의 마이크로 컴퓨터칩을 내장하고 있다. 이 칩은 프로세서, RAM, ROM, 클럭, 버스 그리고 암호전용 코프로세서 등을 포함하고 있다. 따라서 이 칩은 RFID 태그와 비교해서 가격이 비싸고, 복잡하지만 안전한 칩이다. 스마트카드의 주요 응용분야는 전자뱅킹이나 안전한 통신 관련 분야이다. 자바카드는 개방형 플랫폼 중 가장 널리 사용되는데 그 이유는 자바카드의 보안성, 플랫폼 독립성, 그리고 빠른 개발 싸이클 때문이다. 하지만 자바카드는 실행속도가 느리기 때문에 자바 카드의 성능개선은 중요한 연구 분야가 되어왔다. 본 논문에서는 효과적인 트랜잭션버퍼 관리 방법을 제안하여 자바카드의 성능을 개선시켰으며 실험을 통하여 그 성능을 입증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.847-850
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• 2003

An Eye Ball Sensor (EBS) is a system that locates the point where the user gazes on. The conventional EBS using a CCD camera needs many peripherals, software computation causing high cost and power consumption. This paper proposes a compact EBS using smart CMOS Image Sensor (CIS) pixels. The proposed single chip EBS does not need any peripheral and operates at higher speed and lower cost than the conventional EBS. The test chip was designed and fabricated for 32$\times$32 smart CIS pixel array with a 0.35 um CMOS process occupying 5.3$\textrm{mm}^2$ silicon area.

• 한국전기전자재료학회논문지
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• 제29권3호
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• pp.131-134
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• 2016

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.