• Title/Summary/Keyword: Small Scale Grid

Search Result 133, Processing Time 0.025 seconds

SBR-k(Sized-base replacement-k) : File Replacement in Data Grid Environments (SBR-k(Sized-based replacement-k) : 데이터 그리드 환경에서 파일 교체)

  • Park, Hong-Jin
    • The Journal of the Korea Contents Association
    • /
    • v.8 no.11
    • /
    • pp.57-64
    • /
    • 2008
  • The data grid computing provides geographically distributed storage resources to solve computational problems with large-scale data. Unlike cache replacement policies in virtual memory or web-caching replacement, an optimal file replacement policy for data grids is the one of the important problems by the fact that file size is very large. The traditional file replacement policies such as LRU(Least Recently Used), LCB-K(Least Cost Beneficial based on K), EBR(Economic-based cache replacement), LVCT(Least Value-based on Caching Time) have the problem that they have to predict requests or need additional resources to file replacement. To solve theses problems, this paper propose SBR-k(Sized-based replacement-k) that replaces files based on file size. The proposed policy considers file size to reduce the number of files corresponding to a requested file rather than forecasting the uncertain future for replacement. The results of the simulation show that hit ratio was similar when the cache size was small, but the proposed policy was superior to traditional policies when the cache size was large.

An Integrated Face Detection and Recognition System (통합된 시스템에서의 얼굴검출과 인식기법)

  • 박동희;이규봉;이유홍;나상동;배철수
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2003.05a
    • /
    • pp.165-170
    • /
    • 2003
  • This paper presents an integrated approach to unconstrained face recognition in arbitrary scenes. The front end of the system comprises of a scale and pose tolerant face detector. Scale normalization is achieved through novel combination of a skin color segmentation and log-polar mapping procedure. Principal component analysis is used with the multi-view approach proposed in[10] to handle the pose variations. For a given color input image, the detector encloses a face in a complex scene within a circular boundary and indicates the position of the nose. Next, for recognition, a radial grid mapping centered on the nose yields a feature vector within the circular boundary. As the width of the color segmented region provides an estimated size for the face, the extracted feature vector is scale normalized by the estimated size. The feature vector is input to a trained neural network classifier for face identification. The system was evaluated using a database of 20 person's faces with varying scale and pose obtained on different complex backgrounds. The performance of the face recognizer was also quite good except for sensitivity to small scale face images. The integrated system achieved average recognition rates of 87% to 92%.

  • PDF

An Integrated Face Detection and Recognition System (통합된 시스템에서의 얼굴검출과 인식기법)

  • 박동희;배철수
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.7 no.6
    • /
    • pp.1312-1317
    • /
    • 2003
  • This paper presents an integrated approach to unconstrained face recognition in arbitrary scenes. The front end of the system comprises of a scale and pose tolerant face detector. Scale normalization is achieved through novel combination of a skin color segmentation and log-polar mapping procedure. Principal component analysis is used with the multi-view approach proposed in[10] to handle the pose variations. For a given color input image, the detector encloses a face in a complex scene within a circular boundary and indicates the position of the nose. Next, for recognition, a radial grid mapping centered on the nose yields a feature vector within the circular boundary. As the width of the color segmented region provides an estimated size for the face, the extracted feature vector is scale normalized by the estimated size. The feature vector is input to a trained neural network classifier for face identification. The system was evaluated using a database of 20 person's faces with varying scale and pose obtained on different complex backgrounds. The performance of the face recognizer was also quite good except for sensitivity to small scale face images. The integrated system achieved average recognition rates of 87% to 92%.

Airflow modelling studies over the Isle of Arran, Scotland

  • Thielen, J.;Gadian, A.;Vosper, S.;Mobbs, S.
    • Wind and Structures
    • /
    • v.5 no.2_3_4
    • /
    • pp.115-126
    • /
    • 2002
  • A mesoscale meteorological model is applied to simulate turbulent airflow and eddy shedding over the Isle of Arran, SW Scotland, UK. Under conditions of NW flow, the mountain ridge of Kintyre, located upwind of Arran, induces gravity waves that also affect the airflow over the island. The possibility to nest domains allows description of the airflow over Arran with a very high resolution grid, while also including the effects of the surrounding mainland of Scotland, in particular of the mountain ridge of Kintyre. Initialised with a stably stratified NW flow, the mesoscale model simulates quasi-stationary gravity waves over the island induced by Kintyre. Embedded in the larger scale wave trains there is continuous development of small-scale transient eddies, created at the Arran hill tops, that move downstream through the stationary wave field. Although the transient eddies are more frequently simulated on the northern island where the terrain is more pronounced, they are also produced over Tighvein, a hill of 458 m on the southern island where measurements of surface pressure and 2 m meteorological variables have been recorded at intermittent intervals between 1996 and 2000. Comparison between early observations and simulations so far show qualitatively good agreement. Overall the computations demonstrate that turbulent flow can be modelled with a horizontal resolution of 70 m, and describe turbulent eddy structure on wavelength of only a few hundred metres.

BGA to CSP to Flip Chip-Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.8 no.2
    • /
    • pp.37-42
    • /
    • 2001
  • The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

  • PDF

BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • 2001.04a
    • /
    • pp.27-34
    • /
    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

  • PDF

Islanded Microgrid Simulation using Hardware-in-the Loop Simulation (HILS) System based on OPAL-RT (OPAL-RT 기반의 Hardware-in-the-Loop Simulation (HILS) 시스템을 이용한 독립운전모드 마이크로그리드 시뮬레이션)

  • Yoo, Hyeong-Jun;Kim, Hak-Man
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.62 no.4
    • /
    • pp.566-572
    • /
    • 2013
  • A microgrid is a small scale power system. The microgrid is operated in two operation modes, the grid-connected mode and the islanded mode. In the islanded mode, the frequency of a microgrid should be maintained constantly. For this, the balance between power supply and power demand during islanded mode should be met. In general, energy storage systems (ESSs) are used to solve power imbalance. In this paper, the frequency control effect of a Lithium-ion battery energy storage system (Li-ion BESS) has been tested on the hardware-in-the loop simulation (HILS) system environment.

Thermal Fatigue Characteristics of $\mu$ BGA Solder Joints with Underfill (언더필이 적용된 $\mu$p BGA 솔더 접합부의 열피로특성)

  • 고영욱;김종민;이준환;신영의
    • Journal of Welding and Joining
    • /
    • v.21 no.4
    • /
    • pp.25-30
    • /
    • 2003
  • There have been many researches for small scale packages such as CSP, BGA, and Flipchip. Underfill encapsulant technology is one of the latest assembly technologies. The underfill encapsulant could enhance the reliability of the packages by flowing into the gap between die and substrate. In this paper, the effects of underfill packages by both aspects of thermal and mechanical reliabilities are studied. Especially, it is focused to value board-level reliability whether by the underfill is applied or not. First of all, The predicted thermal fatigue lifes of underfilled and no underfilled $\mu$ BGA solder joints are performed by Coffin-Manson's equation and FEA program, ANSYS(version 5.62). Also, the thermal fatigue lifes of $\mu$ BGA solder joints are experimented by thermal cycle test during the temperature, 218K to 423k. Consequently, both experimental and numerical study show that $\mu$ BGA with underfill has over ten times better fatigue lift than $\mu$ BGA without underfill.

The economic based Program for Remote Microgrid Design (경제성평가에 의한 독립형 마이크로그리드의 설계프로그램 개발)

  • Lee, Hak-Ju;Jung, Won-Wook;Chu, Ceol-Min
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
    • /
    • 2009.10a
    • /
    • pp.219-222
    • /
    • 2009
  • Microgrid is a small-scale power system composed of distributed generators, energy storage system and loads, and can operate in the grid-connected mode and the islanded mode. This paper presents optimal design procedures for remote microgrid. The design program is based on the economic evaluations including the feasibility study module, optimal combination and allocation of DER, power network design and the reduction of the GHG emmission. This program which is suggested in this paper shows good performance as a tool of remote microgrid design.

  • PDF

Bayesian curve-fitting with radial basis functions under functional measurement error model

  • Hwang, Jinseub;Kim, Dal Ho
    • Journal of the Korean Data and Information Science Society
    • /
    • v.26 no.3
    • /
    • pp.749-754
    • /
    • 2015
  • This article presents Bayesian approach to regression splines with knots on a grid of equally spaced sample quantiles of the independent variables under functional measurement error model.We consider small area model by using penalized splines of non-linear pattern. Specifically, in a basis functions of the regression spline, we use radial basis functions. To fit the model and estimate parameters we suggest a hierarchical Bayesian framework using Markov Chain Monte Carlo methodology. Furthermore, we illustrate the method in an application data. We check the convergence by a potential scale reduction factor and we use the posterior predictive p-value and the mean logarithmic conditional predictive ordinate to compar models.