• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.272-278
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• 2008

This paper investigated the a-si:H gate driver with the stepwise gate signal. In 1-chip type mobile LCD application the stepwise gate signal for low power consumption can be used by adding simple switching circuit. The power consumption of the a-Si:H gate driver can be decreased by employing the stepwise gate signal in the conventional circuit. In conventional one, the effect of stepwise gate signal can decrease slew rate and increase the fluctuation of gate-off state voltage, In order to increase the slew rate and decrease the gate off state fluctuation, we proposed a new a-Si:H TFT gate driver circuit. The simulation data of the new circuit show that the slew rate and the gate-off state fluctuation are improved, so the circuit can work reliably.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.530-532
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• 2002

We have developed a low-power, high slew-rate OP-AMP for large size and high resolution TFT-LCDs which have 8${\mu}$A quiescent current with settling time less than 6${\mu}$sec. The proposed OP-AMP contains newly developed the driving circuit of class-AB output stage which can achieve a low quiescent current less than 8${\mu}$A and a slew-rate higher than 3.14V/${\mu}$sec.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.3-3
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• 2003

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1108-1110
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• 1995

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Journal of Power Electronics
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• v.4 no.2
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• pp.87-95
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• 2004

A new fast-response high-current clamp DC-DC converter circuit design is presented that will meet the requirements and features of the new generation of microprocessors and digital systems. The clamp in the proposed converter amplifies the current in case of severe load changes and is able to produce high slew rate of output current and capability to keep constant the output voltage. This proposed high-current clamp technique is theoretically loss less, low cost and easy to implement with simple control scheme. This is modified from a basic buck topology by replacing the output inductor with two magnetically coupled inductors. Inductors are difference in inductance, one has large inductance and other has small inductance. The inductor with small inductance will take over the output inductor during fast load transient. It speedup the output current slew rate and reduce the output voltage drop in the case of heavy burden load changes.

• Journal of KSNVE
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• v.5 no.1
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• pp.59-65
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• 1995

In this study, we investigated the operational limit of magnetic bearing-rotor system due to the maximum force limit and slew rjate limit of the electromagnetic actuator as a function of the time dependent control characteristics. The feedback gain of the controller varies the current of the electromagnet coil with the motion of the rotor. The distorsion of magnetic force due to the slew rate limit is not occurred jup to 30, 000 rpm in the magnetic bearing that we have a close relation with the rotational speed and vibration level of the rotor and the proportional gain of the controller. Therefore the maximum force limit determines the maximum allowable orbit radius of the magnetic bearing-rotor system. The maximum allowable vibration levels are exponentially decreased according to the increment of rotational speed and proportional gain of the controller.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.168-172
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• 2005

In this paper, we present a new adaptive biasing scheme for CMOS op-amps. The designed circuit has been used in an Operational Transconductance Amplifier (OTA) with ${\pm}1$ V power supply, and it has improved the positive and negative slew rates from 2.92 V/msec to 1242 V/msec and from 1.56 V/msec to 133 V/msec respectively, while maintaining all the small-signal performance parameter values the same as that without adaptive biasing (as expected), however, there was a marginal decrease of the dynamic range. The most useful features of the proposed circuit are that it uses a very low number of components (thus not creating severe area penalty) and requires only 25 nW of extra stand-by power.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.598-599
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• 2017

In motor application, High efficiency is important. So Design engineer select small gate resistor for lower switching. But There is side effect with small gate resistor. It makes large dv/dt and system request large EMI filter. It makes price increase. This paper introduce about gate drive IC which have solution both of lower loss and EMI issue.