• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.903-906
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• 2003

In this paper, we proposed high slew-rate and low-power OP-AMP of the data driver for TFT-LCDs. Proposed OP-AMP contains newly developed rail-to-rail class-AB input circuit which enables the low-quiescent current and high slew-rate OP-AMP. The slew-rate and the quiescent current of the proposed OP-AMP are 31.2V/$\mu$sec and 5$\mu$A, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1011-1014
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• 2003

We proposed a new two-stage operational amplifier that increases the slew rate by adding some simple circuitry to the conventional structure. The proposed circuit is simulated by HSPICE and the slew rate of the proposed circuit is improved more than 10 times than that of conventional one in slewing state without considerable increments in area and power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.688-696
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• 2014

A slew-rate control method of LCD driver ICs is introduced to increase uniformity between adjacent driver ICs and reduce power consumption. The slew rate of every voltage follower is calibrated by a feedback algorithm during the non-displaying period. Under normal operation mode, the slew rate is dynamically controlled for improving power efficiency. Experimental results show that the power consumption is reduced by 16% with a white pattern and by 10% with a black pattern, and display defects are successfully eliminated.

• 전자공학회논문지B
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• 제32B권5호
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• pp.730-736
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• 1995

This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• 유공압시스템학회논문집
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• 제3권1호
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• pp.7-14
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• 2006

In this paper, an in-process diagnosis method for performance of position control servo system was studied, which was based upon null bias, slew-rate ratio and delay time measurement. Slew-rate ratio and delay time were analyzed by theoretical analysis, computer simulation and experiment. As a result of these analysis, when spool of servovalve was weared, slew-rate ratio was decreased and delay time was increased.

• 한국전자통신학회논문지
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• 제18권4호
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• pp.571-578
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• 2023

본 논문에서는 차내 통신을 위한 데이터 송신기에 지연고정루프를 접목한 회로를 제안한다. 낮은 전자기 간섭 특성을 가진 송신기의 설계를 위해 낮은 슬루율을 가지며, 회로 소자의 공정에 따른 변화로 인한 슬루율 변화량을 보정할 수 있는 지연고정루프를 적용하였다. 시뮬레이션 결과에 의하면, 지연고정루프가 적용된 송신기는 기존의 송신기보다 낮은 슬루율 변화량을 가진다. 제안한 구조의 회로는 65nm 공정으로 설계되었으며, 데이터 전송속도는 20Mbps, 공급전압은 1.1V이다. 지연고정루프가 있는 송신기는 기존의 송신기에 대비하여 빠른 조건에서 53.6% 낮은 슬루율 변화량, 느린 조건에서 13.07% 낮은 슬루율 변화량을 가진다.

• 한국정보통신학회논문지
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• 제23권4호
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• pp.431-437
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• 2019

전력선 통신(PLC: Power Line Communication)은 저비용으로 고속 전송이 가능하여 스마트 그리드와 연계하여 다양하게 활용되고 있다. 그러나 전력선 채널은 임펄스 잡음으로 인하여 많은 문제가 있어 이를 해결하기 위하여 다양한 연구가 진행되어 왔다. 최근에는 아날로그 신호에 대한 비선형 필터에 적응형 clippling을 사용하는 ACDL(Adaptive Cannonical Differential Limiter)이 제안되었다. 본 논문에서는 이의 특성을 분석하고 간략화하여 오버샘플링된 디지털신호에 대해 slew rate를 검출하는 방안과 유사함을 보였다. 제안된 방식은 모의 실험으로 PRIME 표준에서 성능을 검증하여 ACDL과 동일 수준 이상의 성능을 가지면서도 훨씬 간단히 구현이 가능한 장점을 확인하였다. BER 성능은 동등하면서도 복잡도는 10%이하로 줄어든다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2006년도 ISMP 2006
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• pp.293-316
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• 2006

[ $\blacksquare$ ] I/O Signal $\square$ We see adequate margin for the RC B design $\square$ Minimum ODW value is 328ps using Ac to DC measurement for the read case. $\square$ Minimum ODW value is 350ps using AC to DC mesurement method for the write case. $\blacksquare$ CLK Signal $\square$ The slew-rate decreases when the Cterm value increases $\square$ Lower slew-rate could effect delay and jitter. $\square$ There are some ldge issues during transitions with lower Cterm and without Cterm. $\square$ Our recommendation for the Cterm value range is between 1.5pF to 2.4pF. $\blacksquare$ ADD/CMD/Ctrl Signal $\square$ High output slew-rate at low VDD causes ring back that reduces voltage margin because of x-talk. $\square$ 30ohm Rterm for the CTRL signal shows a better signal integrity result compared to 36ohm.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.