• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Applied Chemistry for Engineering
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• v.31 no.3
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• pp.291-298
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• 2020

ZITO/Ag/ZITO multilayer transparent electrodes at room temperature on glass substrates were prepared using RF/DC magnetron sputtering. Transparent conductive films with a sheet resistance of 9.4 Ω/㎡ and a transmittance of 83.2% at 550 nm were obtained for the multilayer structure comprising ZITO/Ag/ZITO (100/8/42 nm). The sheet resistance and transmittance of ZITO/Ag/ZITO multilayer films meant that they would be highly applicable for use in polymer-dispersed liquid crystal (PDLC)-based smart windows due to the ability to effectively block infrared rays (heat rays) and thereby act as an energy-saving smart glass. Effects of the thickness of the PDLC layer and the intensity of ultraviolet light (UV) on electro-optical properties, photopolymerization kinetics, and morphologies of difunctional urethane acrylate-based PDLC systems were investigated using new transparent conducting electrodes. A PDLC cell photo-cured using UV at an intensity of 2.0 mW/c㎡ with a 15 ㎛-thick PDLC layer showed outstanding off-state opacity, good on-state transmittance, and favorable driving voltage. Also, the PDLC-based smart window optimized in this study formed liquid crystal droplets with a favorable microstructure, having an average size range of 2~5 ㎛ for scattering light efficiently, which could contribute to its superior final performance.

• Journal of the Korea Convergence Society
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• v.9 no.9
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• pp.183-189
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• 2018

This study deals with the design and development of imaging optics having 24mm focal length for MWIR ($3{\sim}5{\mu}m$) with two symmetrical lenses facing each other. We used CodeV in our optical design, and we performed the optimization process to have the resolution and angle of view satisfying the user's requirements. The materials of lenses were limited to two types, including KCIR035 with a refractive index of 1.7589, developed in Korea. The optical system designed in this way consists of two aspherical lenses made of KCIR035 material having the same shape and one spherical lens made of Si. Here, the arrangement of the two aspherical lenses is characterized by having a symmetrical structure facing each other. And this optical system has a resolution of MTF value of 0.35 or more at a line width of 20 lp / mm. Therefore, it is considered that this optical system has the capability to be applied to a thermal imaging camera using a $206{\times}156$ array MWIR detection device having a pixel size of $25{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Journal of the Korean Operations Research and Management Science Society
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• v.17 no.1
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• pp.117-117
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• 1992

Pubilc utility industries including the electric utility industry are facing a new stream of privatization com-petition with the private sector and deregulation. The necewssity to solve now and in the future power supply and demand problems has been increasing through the sophisticated generation expansion plan(GEP) approach con-sidering not only KEPCo's supply-side resources but also outside resources such as non-utility generation(NUG) demand-side management (DSM). Under the environmental situation in the current electric utility industry a new approach is needed to acquire multiple resources competitively. This study presents the development of a modified electric generation expansion analysis system(EGEAS) model with avoided cost based on the existing EGEAS model which is a dynamic program to develope an optimal generation expansion plan for the electric utility. We are trying to find optimal GEP in Korea's case using our modified model and observe the difference for the level of reliabilities such as the reserve margin(RM) loss of load probability(LOLP) and expected unserved energy percent(EUEP) between the existing EGEAS model and our model. In addition we are trying to calculate avoided cost for NUG resources which is a criterion to evaluate herem and test possibility of connection calculation of avoided cost with GEP implementation using our modified model. The results of our case study are as follows. First we were able to find that the generation expansion plan and reliability measures were largely influenced by capacity size and loading status of NUG resources, Second we were able to find that avoided cost which are criteria to evaluate NUG resources could be calculated by using our modified EGEAS model with avoided cost. We also note that avoided costs were calculated by our model in connection with generation expansion plans.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.5
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• pp.385-391
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• 2013

Big Data is data of big size which is not processed, collected, stored, searched, analyzed by the existing database management system. The parallel genetic algorithm using the Hadoop for BigData technology is easily realized by implementing GA(Genetic Algorithm) using MapReduce in the Hadoop Distribution System. The previous study that the genetic algorithm using MapReduce is proposed suitable transforming for the GA by MapReduce. However, they did not show good performance because of frequently occurring data input and output. In this paper, we proposed the MRPGA(MapReduce Parallel Genetic Algorithm) using improvement Map and Reduce process and the parallel processing characteristic of MapReduce. The optimal solution can be found by using the topology, migration of parallel genetic algorithm and local search algorithm. The convergence speed of the proposal method is 1.5 times faster than that of the existing MapReduce SGA, and is the optimal solution can be found quickly by the number of sub-generation iteration. In addition, the MRPGA is able to improve the processing and analysis performance of Big Data technology.

• Korean Chemical Engineering Research
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• v.55 no.4
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• pp.542-547
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• 2017

Ultrasound-assisted extraction (UAE) has attracted growing interest, as it is an effective method for the rapid extraction of bioactive compounds from plants with a high extraction efficiency comparable to the conventional extraction. In this study, UAE was used for the extraction of polyphenols from lipid extracted microalgae (Tetraselmis KCTC 12236BP) and the effects of five extraction variables on the total phenolic compounds (TPC) were studied. For the optimization of extraction parameters, particle size, solid-to-liquid (L/S) ratio, ethanol concentration, extraction temperature and extraction time have been examined as independent variables. All variables exhibited the significant effects on the extraction of TPC and extraction temperature showed the most significant effect among five variables. The optimal extraction conditions were the extraction using mixed particle, S/L ratio of 10%, ethanol concentration of 60%, extraction temperature of $100^{\circ}C$ and extraction time of 30 min, which gave the 8.7 mg GAE/g DW for TPC. Compared with conventional hot-water extraction, TPC extraction under UAE was increased by up to 1.8 fold with same extraction condition. This study showed that UAE under low temperature and short extraction time was proven to be an effective extraction process for TPC production from LEA compared to conventional hot-water extraction process.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.3
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• pp.230-236
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• 2020

A trash screen is installed in front of the inflow channel of a drainage pumping station, sewage treatment plant, and a power plant to block floating contaminants. The bottleneck phenomenon, which decreases the water inflow, causes damage to the damper as a result of clogging in between the screen if string type obstacles are not removed. In this paper, the apron was removed, and the screen was expanded, to prevent breakage of the bottleneck phenomenon and string type obstacles. This was designed using an extended rake by adding an inner rake in between the screen interspace to remove the bottleneck phenomenon and string type obstacles. To design the inner rake that satisfies the allowable stresses of the existing damper rake, the experiment points were determined according to the experimental design method using the inner rake vertical length and the thickness of the reinforced section as parameters. The use of the ANSYS static structural module and statistical analysis tool R software gives the optimized shape according to the response surface method. The relative error between the response surface analysis results and the simulation results was 1.63% of the determined optimal design-point rake length of 210.2 mm and the reinforcement section thickness of 2 mm. Through empirical experiments, a test rake was constructed to the actual size, and approximately 97% of the bottleneck phenomenon and string type obstacles could be removed.

• The Journal of the Korea Contents Association
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• v.8 no.5
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• pp.72-81
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• 2008

High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.