• Journal of Power Electronics
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• v.7 no.2
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• pp.174-180
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• 2007

In this paper, a simple control method for two-stage utility grid-connected photovoltaic power conditioning systems (PCS) is proposed. This approach enables maximum power point (MPP) tracking control with post-stage inverter current information instead of calculating solar array power, which significantly simplifies the controller and the sensor. Furthermore, there is no feedback loop in the pre-stage converter to control the solar array voltage or current because the MPP tracker drives the converter switch duty cycle. This simple PCS control strategy can reduce the cost and size, and can be utilized with a low cost digital processor. For verification of the proposed control strategy, a 2.5kW two-stage photovoltaic grid-connected PCS hardware which consists of a boost converter cascaded with a single-phase inverter was built and tested.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.348-350
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• 1996

A new reset winding clamped forward converter with transformer voltage feedback technique for power factor correction with a single-switch/single-stage is proposed. The proposed converter gives the good power factor correction, low current harmonic distortions, and tight output voltage regulation. The prototype shows the IEC555-2 requirements are met satisfactorily with nearly unity power factor.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.200-203
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• 2002

This paper presents Continuous-current mode of $S^4$-PFC(Single-Stage Single-switch Power Factor Correction) converter. Proposed converter operates in the continueous current mode(CCM) at full load and discontinuous current mode(DCM) at light load. So, characteristic of proposed converter is no bus voltage stress and Zero Voltage Switching(ZVS) using resonant auxiliary circuit. And. This paper presents characteristic of $S^4$-PFC converter and effect of circuit parameter of proposed converter through the input inductor, PFC capacitor's variation. All of these theory and characteristic verified through the experiment with a 72W(12V, 6A), $90^{kHz}$ prototype converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.539-546
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• 1999

A new integrated single-stage zero current switched(ZCS) quasi resonant convertedQRC) for the IX)wer f factor correction(PFCl converter is introduced in this paper. The power factor correction can be achieved by t the discontinuous conduction mod$\varepsilon$(DCM) operation of an input current. The proposed converter has the c characteristics of the good IX)wer factor, 10씨 line current harmonics, and tight output regulation. Furthern10re, t the ringing effect due to the output capacitance of the main switch can be eliminated by use of‘ active clamp c circuit. Therefore, the proIX)sed converter is expecttc'(] to be suitable for a compact power converter with a t tightly regulated output voltage requiring a switching frequency of more than several hundrtc'(]s kHz.

• Journal of Power Electronics
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• v.17 no.1
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• pp.222-231
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• 2017

In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

• The Journal of Korean Institute of Information Technology
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• v.16 no.11
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• pp.23-34
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• 2018

This paper presents the high efficiency and high power-factor power supply for LED lighting equipment. The proposed power supply is the single-stage power structure consisted of the full-bridge diode rectifier and flyback converter, and thus the power-factor correction and output voltage regulation are performed simultaneously using only one controller IC and one power semiconductor switch. Furthermore, the proposed power supply reduces the voltage stress and switching loss of main switch using the regenerative snubber, and it improves the system efficiency using the synchronous rectifier. The applied synchronous rectifier is the new voltage-driven type and its operation and construction are simple. In this paper, the operation principle of proposed power supply is explained through the operation analyses of its power-factor correction and main power conversion parts and the operation of synchronous rectifier is described, briefly. Also, a design example of the power circuit of 40W-class prototype is shown and the operation characteristics of proposed power supply are validated through the experimental results of the implemented prototype by the designed circuit parameter.

• Journal of Power Electronics
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• v.18 no.3
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• pp.694-701
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• 2018

This paper proposes a new single-phase power converter topology for changing the frequency of AC voltage. The proposed single-phase frequency converter (SFC) includes a T-type multi-level power converter (TMPC), a frequency decoupling transformer (FDT) and a digital signal processor (DSP). The TMPC can convert a 60 Hz AC voltage to a DC voltage and then convert the DC voltage to a 50 Hz AC voltage. Therefore, the output currents of the two T-type power switch arms have 50 Hz and 60 Hz components. The FDT is used to decouple the 50 Hz and 60 Hz components. The salient feature of the proposed SFC is that only one power electronic converter stage is used since the functions of the AC-DC and DC-AC power conversions are integrated into the TMPC. Therefore, the proposed SFC can simplify both the power circuit and the control circuit. In order to verify the functions of the proposed SFC, a hardware prototype is established. Experimental results verify that the performance of the proposed SFC is as expected.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.3
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• pp.263-269
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• 2013

The flyback converter has been applied widely in isolated DC/DC power converters because this converters employ a single MOSFET switch. The leakage inductance should be minimized for high efficiency of flyback converter. but in reality, it is very difficult. Namely, The Snubber circuit is essential to recover the leakage inductance stored energy when the switch is turn off. Flyback Converter typically operates in DCM mode and when switch is turn off in hard switching, this hard switching action results in a high power losses and switching stresses. In order to overcome these problems, a novel soft switching flyback converter using resonant snubber circuit is proposed in this paper. The resonant snubber circuit is composed of the transformer leakage inductance and a capacitor. To verify and confirm the proposed resonant snubber circuit, PSIM simulation and hardware prototype are implemented. Simulation and Experimental results indicate that the proposed resonant snubber circuit is effective.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.